[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp TargetLowering.cpp
Dan Gohman
djg at cray.com
Thu Jun 21 07:42:45 PDT 2007
Changes in directory llvm/lib/CodeGen/SelectionDAG:
SelectionDAGISel.cpp updated: 1.466 -> 1.467
TargetLowering.cpp updated: 1.119 -> 1.120
---
Log message:
Rename TargetLowering::getNumElements and friends to
TargetLowering::getNumRegisters and similar, to avoid confusion with
the actual number of elements for vector types.
---
Diffs of the changes: (+19 -19)
SelectionDAGISel.cpp | 28 ++++++++++++++--------------
TargetLowering.cpp | 10 +++++-----
2 files changed, 19 insertions(+), 19 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.466 llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.467
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.466 Fri Jun 15 17:26:58 2007
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Thu Jun 21 09:42:22 2007
@@ -290,19 +290,19 @@
if (PN->use_empty()) continue;
MVT::ValueType VT = TLI.getValueType(PN->getType());
- unsigned NumElements;
+ unsigned NumRegisters;
if (VT != MVT::Vector)
- NumElements = TLI.getNumElements(VT);
+ NumRegisters = TLI.getNumRegisters(VT);
else {
MVT::ValueType VT1,VT2;
- NumElements =
+ NumRegisters =
TLI.getVectorTypeBreakdown(cast<VectorType>(PN->getType()),
VT1, VT2);
}
unsigned PHIReg = ValueMap[PN];
assert(PHIReg && "PHI node does not have an assigned virtual register!");
const TargetInstrInfo *TII = TLI.getTargetMachine().getInstrInfo();
- for (unsigned i = 0; i != NumElements; ++i)
+ for (unsigned i = 0; i != NumRegisters; ++i)
BuildMI(MBB, TII->get(TargetInstrInfo::PHI), PHIReg+i);
}
}
@@ -343,7 +343,7 @@
// The common case is that we will only create one register for this
// value. If we have that case, create and return the virtual register.
- unsigned NV = TLI.getNumElements(VT);
+ unsigned NV = TLI.getNumRegisters(VT);
if (NV == 1) {
// If we are promoting this value, pick the next largest supported type.
MVT::ValueType PromotedType = TLI.getTypeToTransformTo(VT);
@@ -750,7 +750,7 @@
// Source must be expanded. This input value is actually coming from the
// register pair InReg and InReg+1.
MVT::ValueType DestVT = TLI.getTypeToExpandTo(VT);
- unsigned NumVals = TLI.getNumElements(VT);
+ unsigned NumVals = TLI.getNumRegisters(VT);
N = DAG.getCopyFromReg(DAG.getEntryNode(), InReg, DestVT);
if (NumVals == 1)
N = DAG.getNode(ISD::BIT_CONVERT, VT, N);
@@ -3185,7 +3185,7 @@
unsigned NumRegs = 1;
if (OpInfo.ConstraintVT != MVT::Other)
- NumRegs = TLI.getNumElements(OpInfo.ConstraintVT);
+ NumRegs = TLI.getNumRegisters(OpInfo.ConstraintVT);
MVT::ValueType RegVT;
MVT::ValueType ValueVT = OpInfo.ConstraintVT;
@@ -3831,7 +3831,7 @@
// integers. Figure out what the destination type is and how many small
// integers it turns into.
MVT::ValueType NVT = getTypeToExpandTo(VT);
- unsigned NumVals = getNumElements(VT);
+ unsigned NumVals = getNumRegisters(VT);
for (unsigned i = 0; i != NumVals; ++i) {
RetVals.push_back(NVT);
// if it isn't first piece, alignment must be 1
@@ -4088,7 +4088,7 @@
// integers. Figure out what the source elt type is and how many small
// integers it is.
MVT::ValueType NVT = getTypeToExpandTo(VT);
- unsigned NumVals = getNumElements(VT);
+ unsigned NumVals = getNumRegisters(VT);
for (unsigned i = 0; i != NumVals; ++i)
RetTys.push_back(NVT);
} else {
@@ -4507,7 +4507,7 @@
return DAG.getCopyToReg(getRoot(), Reg, Op);
} else {
DestVT = TLI.getTypeToExpandTo(SrcVT);
- unsigned NumVals = TLI.getNumElements(SrcVT);
+ unsigned NumVals = TLI.getNumRegisters(SrcVT);
if (NumVals == 1)
return DAG.getCopyToReg(getRoot(), Reg,
DAG.getNode(ISD::BIT_CONVERT, DestVT, Op));
@@ -4695,16 +4695,16 @@
// Remember that this register needs to added to the machine PHI node as
// the input for this MBB.
MVT::ValueType VT = TLI.getValueType(PN->getType());
- unsigned NumElements;
+ unsigned NumRegisters;
if (VT != MVT::Vector)
- NumElements = TLI.getNumElements(VT);
+ NumRegisters = TLI.getNumRegisters(VT);
else {
MVT::ValueType VT1,VT2;
- NumElements =
+ NumRegisters =
TLI.getVectorTypeBreakdown(cast<VectorType>(PN->getType()),
VT1, VT2);
}
- for (unsigned i = 0, e = NumElements; i != e; ++i)
+ for (unsigned i = 0, e = NumRegisters; i != e; ++i)
PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i));
}
}
Index: llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp:1.119 llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp:1.120
--- llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp:1.119 Wed May 30 11:30:06 2007
+++ llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp Thu Jun 21 09:42:22 2007
@@ -216,7 +216,7 @@
// Everything defaults to one.
for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i)
- NumElementsForVT[i] = 1;
+ NumRegistersForVT[i] = 1;
// Find the largest integer register class.
unsigned LargestIntReg = MVT::i128;
@@ -227,12 +227,12 @@
// many registers to represent as the previous ValueType.
unsigned ExpandedReg = LargestIntReg; ++LargestIntReg;
for (++ExpandedReg; MVT::isInteger((MVT::ValueType)ExpandedReg);++ExpandedReg)
- NumElementsForVT[ExpandedReg] = 2*NumElementsForVT[ExpandedReg-1];
+ NumRegistersForVT[ExpandedReg] = 2*NumRegistersForVT[ExpandedReg-1];
// Inspect all of the ValueType's possible, deciding how to process them.
for (unsigned IntReg = MVT::i1; IntReg <= MVT::i128; ++IntReg)
// If we are expanding this type, expand it!
- if (getNumElements((MVT::ValueType)IntReg) != 1)
+ if (getNumRegisters((MVT::ValueType)IntReg) != 1)
SetValueTypeAction((MVT::ValueType)IntReg, Expand, *this, TransformToType,
ValueTypeActions);
else if (!isTypeLegal((MVT::ValueType)IntReg))
@@ -250,7 +250,7 @@
if (isTypeLegal(MVT::f64))
TransformToType[MVT::f64] = MVT::f64;
else {
- NumElementsForVT[MVT::f64] = NumElementsForVT[MVT::i64];
+ NumRegistersForVT[MVT::f64] = NumRegistersForVT[MVT::i64];
SetValueTypeAction(MVT::f64, Expand, *this, TransformToType,
ValueTypeActions);
}
@@ -260,7 +260,7 @@
SetValueTypeAction(MVT::f32, Promote, *this, TransformToType,
ValueTypeActions);
else {
- NumElementsForVT[MVT::f32] = NumElementsForVT[MVT::i32];
+ NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::i32];
SetValueTypeAction(MVT::f32, Expand, *this, TransformToType,
ValueTypeActions);
}
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