[llvm-commits] CVS: llvm/lib/Target/ARM/ARMInstrInfo.cpp ARMInstrInfo.h ARMInstrInfo.td ARMInstrThumb.td

[Dan Gohman]

Changes in directory llvm/lib/Target/ARM:

ARMInstrInfo.cpp updated: 1.38 -> 1.39
ARMInstrInfo.h updated: 1.15 -> 1.16
ARMInstrInfo.td updated: 1.111 -> 1.112
ARMInstrThumb.td updated: 1.31 -> 1.32
---
Log message:

Replace M_REMATERIALIZIBLE and the newly-added isOtherReMaterializableLoad
with a general target hook to identify rematerializable instructions. Some
instructions are only rematerializable with specific operands, such as loads
from constant pools, while others are always rematerializable. This hook
allows both to be identified as being rematerializable with the same
mechanism.


---
Diffs of the changes:  (+15 -5)

 ARMInstrInfo.cpp |   14 ++++++++++++++
 ARMInstrInfo.h   |    1 +
 ARMInstrInfo.td  |    4 ----
 ARMInstrThumb.td |    1 -
 4 files changed, 15 insertions(+), 5 deletions(-)


Index: llvm/lib/Target/ARM/ARMInstrInfo.cpp
diff -u llvm/lib/Target/ARM/ARMInstrInfo.cpp:1.38 llvm/lib/Target/ARM/ARMInstrInfo.cpp:1.39
--- llvm/lib/Target/ARM/ARMInstrInfo.cpp:1.38	Mon Jun 18 20:25:30 2007
+++ llvm/lib/Target/ARM/ARMInstrInfo.cpp	Mon Jun 18 20:48:04 2007
@@ -130,6 +130,20 @@
   return 0;
 }
 
+bool ARMInstrInfo::isTriviallyReMaterializable(MachineInstr *MI) const {
+  switch (MI->getOpcode()) {
+  default: break;
+  case ARM::LDRcp:
+  case ARM::MOVi:
+  case ARM::MVNi:
+  case ARM::MOVi2pieces:
+  case ARM::tLDRcp:
+    // These instructions are always trivially rematerializable.
+    return true;
+  }
+  return false;
+}
+
 static unsigned getUnindexedOpcode(unsigned Opc) {
   switch (Opc) {
   default: break;


Index: llvm/lib/Target/ARM/ARMInstrInfo.h
diff -u llvm/lib/Target/ARM/ARMInstrInfo.h:1.15 llvm/lib/Target/ARM/ARMInstrInfo.h:1.16
--- llvm/lib/Target/ARM/ARMInstrInfo.h:1.15	Mon Jun 18 20:25:30 2007
+++ llvm/lib/Target/ARM/ARMInstrInfo.h	Mon Jun 18 20:48:04 2007
@@ -87,6 +87,7 @@
                            unsigned &SrcReg, unsigned &DstReg) const;
   virtual unsigned isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const;
   virtual unsigned isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) const;
+  virtual bool isTriviallyReMaterializable(MachineInstr *MI) const;
   
   virtual MachineInstr *convertToThreeAddress(MachineFunction::iterator &MFI,
                                               MachineBasicBlock::iterator &MBBI,


Index: llvm/lib/Target/ARM/ARMInstrInfo.td
diff -u llvm/lib/Target/ARM/ARMInstrInfo.td:1.111 llvm/lib/Target/ARM/ARMInstrInfo.td:1.112
--- llvm/lib/Target/ARM/ARMInstrInfo.td:1.111	Mon Jun 18 20:25:30 2007
+++ llvm/lib/Target/ARM/ARMInstrInfo.td	Mon Jun 18 20:48:04 2007
@@ -670,7 +670,6 @@
                [(set GPR:$dst, (load addrmode2:$addr))]>;
 
 // Special LDR for loads from non-pc-relative constpools.
-let isReMaterializable = 1 in
 def LDRcp : AI2<(ops GPR:$dst, addrmode2:$addr),
                  "ldr", " $dst, $addr", []>;
 
@@ -804,7 +803,6 @@
 def MOVs : AI1<(ops GPR:$dst, so_reg:$src),
                 "mov", " $dst, $src", [(set GPR:$dst, so_reg:$src)]>;
 
-let isReMaterializable = 1 in
 def MOVi : AI1<(ops GPR:$dst, so_imm:$src),
                 "mov", " $dst, $src", [(set GPR:$dst, so_imm:$src)]>;
 
@@ -912,7 +910,6 @@
                 "mvn", " $dst, $src", [(set GPR:$dst, (not GPR:$src))]>;
 def  MVNs  : AI<(ops GPR:$dst, so_reg:$src),
                 "mvn", " $dst, $src", [(set GPR:$dst, (not so_reg:$src))]>;
-let isReMaterializable = 1 in
 def  MVNi  : AI<(ops GPR:$dst, so_imm:$imm),
                 "mvn", " $dst, $imm", [(set GPR:$dst, so_imm_not:$imm)]>;
 
@@ -1183,7 +1180,6 @@
 // Large immediate handling.
 
 // Two piece so_imms.
-let isReMaterializable = 1 in
 def MOVi2pieces : AI1x2<(ops GPR:$dst, so_imm2part:$src),
                          "mov", " $dst, $src",
                          [(set GPR:$dst, so_imm2part:$src)]>;


Index: llvm/lib/Target/ARM/ARMInstrThumb.td
diff -u llvm/lib/Target/ARM/ARMInstrThumb.td:1.31 llvm/lib/Target/ARM/ARMInstrThumb.td:1.32
--- llvm/lib/Target/ARM/ARMInstrThumb.td:1.31	Mon Jun 18 20:25:30 2007
+++ llvm/lib/Target/ARM/ARMInstrThumb.td	Mon Jun 18 20:48:04 2007
@@ -267,7 +267,6 @@
                   [(set GPR:$dst, (load (ARMWrapper tconstpool:$addr)))]>;
 
 // Special LDR for loads from non-pc-relative constpools.
-let isReMaterializable = 1 in
 def tLDRcp  : TIs<(ops GPR:$dst, i32imm:$addr),
                   "ldr $dst, $addr", []>;
 } // isLoad