[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp

[Chris Lattner]

Changes in directory llvm/lib/CodeGen/SelectionDAG:

SelectionDAGISel.cpp updated: 1.464 -> 1.465
---
Log message:

Fix CodeGen/X86/inline-asm-x-scalar.ll:test4, by retaining regclass info
for tied register constraints.



---
Diffs of the changes:  (+9 -6)

 SelectionDAGISel.cpp |   15 +++++++++------
 1 files changed, 9 insertions(+), 6 deletions(-)


Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.464 llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.465
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.464	Fri Jun 15 14:04:19 2007
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp	Fri Jun 15 14:11:01 2007
@@ -3222,7 +3222,8 @@
   // Otherwise, if this was a reference to an LLVM register class, create vregs
   // for this reference.
   std::vector<unsigned> RegClassRegs;
-  if (PhysReg.second) {
+  const TargetRegisterClass *RC = PhysReg.second;
+  if (RC) {
     // If this is an early clobber or tied register, our regalloc doesn't know
     // how to maintain the constraint.  If it isn't, go ahead and create vreg
     // and let the regalloc do the right thing.
@@ -3272,11 +3273,13 @@
     
     // Check to see if this register is allocatable (i.e. don't give out the
     // stack pointer).
-    const TargetRegisterClass *RC = isAllocatableRegister(Reg, MF, TLI, MRI);
-    if (!RC) {
-      // Make sure we find consecutive registers.
-      NumAllocated = 0;
-      continue;
+    if (RC == 0) {
+      RC = isAllocatableRegister(Reg, MF, TLI, MRI);
+      if (!RC) {        // Couldn't allocate this register.
+        // Reset NumAllocated to make sure we return consecutive registers.
+        NumAllocated = 0;
+        continue;
+      }
     }
     
     // Okay, this register is good, we can use it.