[llvm-commits] CVS: llvm/utils/TableGen/RegisterInfoEmitter.cpp CodeGenTarget.cpp CodeGenRegisters.h

[Christopher Lamb]

Changes in directory llvm/utils/TableGen:

RegisterInfoEmitter.cpp updated: 1.56 -> 1.57
CodeGenTarget.cpp updated: 1.91 -> 1.92
CodeGenRegisters.h updated: 1.11 -> 1.12
---
Log message:

Add support to tablegen for specifying subregister classes on a per register class basis.


---
Diffs of the changes:  (+50 -0)

 CodeGenRegisters.h      |    1 +
 CodeGenTarget.cpp       |   10 ++++++++++
 RegisterInfoEmitter.cpp |   39 +++++++++++++++++++++++++++++++++++++++
 3 files changed, 50 insertions(+)


Index: llvm/utils/TableGen/RegisterInfoEmitter.cpp
diff -u llvm/utils/TableGen/RegisterInfoEmitter.cpp:1.56 llvm/utils/TableGen/RegisterInfoEmitter.cpp:1.57
--- llvm/utils/TableGen/RegisterInfoEmitter.cpp:1.56	Mon Jun  4 18:52:59 2007
+++ llvm/utils/TableGen/RegisterInfoEmitter.cpp	Wed Jun 13 17:20:15 2007
@@ -224,6 +224,44 @@
          
     std::map<unsigned, std::set<unsigned> > SuperClassMap;
     OS << "\n";
+    
+    
+    // Emit the sub-register classes for each RegisterClass
+    for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
+      const CodeGenRegisterClass &RC = RegisterClasses[rc];
+
+      // Give the register class a legal C name if it's anonymous.
+      std::string Name = RC.TheDef->getName();
+
+      OS << "  // " << Name 
+         << " Sub-register Classess...\n"
+         << "  static const TargetRegisterClass* const "
+         << Name << "SubRegClasses [] = {\n    ";
+
+      bool Empty = true;
+      
+      for (unsigned subrc = 0, e2 = RC.SubRegClasses.size();
+            subrc != e2; ++subrc) {
+        unsigned rc2 = 0, e2 = RegisterClasses.size();
+        for (; rc2 != e2; ++rc2) {
+          const CodeGenRegisterClass &RC2 =  RegisterClasses[rc2];
+          if (RC.SubRegClasses[subrc]->getName() == RC2.getName()) {
+            if (!Empty) OS << ", ";
+              OS << "&" << getQualifiedName(RC2.TheDef) << "RegClass";
+            Empty = false;
+            break;
+          }
+        }
+        if (rc2 == e2)
+          throw "Register Class member '" + 
+            RC.SubRegClasses[subrc]->getName() + 
+            "' is not a valid RegisterClass!";
+      }
+
+      OS << (!Empty ? ", " : "") << "NULL";
+      OS << "\n  };\n\n";
+    }
+    
     // Emit the sub-classes array for each RegisterClass
     for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
       const CodeGenRegisterClass &RC = RegisterClasses[rc];
@@ -304,6 +342,7 @@
          << RC.getName() + "VTs" << ", "
          << RC.getName() + "Subclasses" << ", "
          << RC.getName() + "Superclasses" << ", "
+         << RC.getName() + "SubRegClasses" << ", "
          << RC.SpillSize/8 << ", "
          << RC.SpillAlignment/8 << ", " << RC.getName() << ", "
          << RC.getName() << " + " << RC.Elements.size() << ") {}\n";


Index: llvm/utils/TableGen/CodeGenTarget.cpp
diff -u llvm/utils/TableGen/CodeGenTarget.cpp:1.91 llvm/utils/TableGen/CodeGenTarget.cpp:1.92
--- llvm/utils/TableGen/CodeGenTarget.cpp:1.91	Wed Jun  6 05:14:55 2007
+++ llvm/utils/TableGen/CodeGenTarget.cpp	Wed Jun 13 17:20:15 2007
@@ -199,6 +199,16 @@
     Elements.push_back(Reg);
   }
   
+  std::vector<Record*> SubRegClassList = 
+                        R->getValueAsListOfDefs("SubRegClassList");
+  for (unsigned i = 0, e = SubRegClassList.size(); i != e; ++i) {
+    Record *SubRegClass = SubRegClassList[i];
+    if (!SubRegClass->isSubClassOf("RegisterClass"))
+      throw "Register Class member '" + SubRegClass->getName() +
+            "' does not derive from the RegisterClass class!";
+    SubRegClasses.push_back(SubRegClass);
+  }  
+  
   // Allow targets to override the size in bits of the RegisterClass.
   unsigned Size = R->getValueAsInt("Size");
 


Index: llvm/utils/TableGen/CodeGenRegisters.h
diff -u llvm/utils/TableGen/CodeGenRegisters.h:1.11 llvm/utils/TableGen/CodeGenRegisters.h:1.12
--- llvm/utils/TableGen/CodeGenRegisters.h:1.11	Thu Dec 29 18:12:56 2005
+++ llvm/utils/TableGen/CodeGenRegisters.h	Wed Jun 13 17:20:15 2007
@@ -38,6 +38,7 @@
     std::vector<MVT::ValueType> VTs;
     unsigned SpillSize;
     unsigned SpillAlignment;
+    std::vector<Record*> SubRegClasses;
     std::string MethodProtos, MethodBodies;
 
     const std::string &getName() const;