[llvm-commits] CVS: llvm/lib/Target/ARM/ARMInstrInfo.cpp

[Evan Cheng]

Changes in directory llvm/lib/Target/ARM:

ARMInstrInfo.cpp updated: 1.28 -> 1.29
---
Log message:

BlockHasNoFallThrough() now returns true if block ends with a return instruction; AnalyzeBranch() should ignore predicated instructionsd.

---
Diffs of the changes:  (+13 -2)

 ARMInstrInfo.cpp |   15 +++++++++++++--
 1 files changed, 13 insertions(+), 2 deletions(-)


Index: llvm/lib/Target/ARM/ARMInstrInfo.cpp
diff -u llvm/lib/Target/ARM/ARMInstrInfo.cpp:1.28 llvm/lib/Target/ARM/ARMInstrInfo.cpp:1.29
--- llvm/lib/Target/ARM/ARMInstrInfo.cpp:1.28	Thu May 17 19:18:17 2007
+++ llvm/lib/Target/ARM/ARMInstrInfo.cpp	Mon May 21 13:56:31 2007
@@ -298,6 +298,11 @@
   return NewMIs[0];
 }
 
+static bool isPredicated(MachineInstr *MI) {
+  MachineOperand *PMO = MI->findFirstPredOperand();
+  return PMO && PMO->getImmedValue() != ARMCC::AL;
+}
+
 // Branch analysis.
 bool ARMInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
                                  MachineBasicBlock *&FBB,
@@ -312,7 +317,8 @@
   
   // If there is only one terminator instruction, process it.
   unsigned LastOpc = LastInst->getOpcode();
-  if (I == MBB.begin() || !isTerminatorInstr((--I)->getOpcode())) {
+  if (I == MBB.begin() ||
+      isPredicated(--I) || !isTerminatorInstr(I->getOpcode())) {
     if (LastOpc == ARM::B || LastOpc == ARM::tB) {
       TBB = LastInst->getOperand(0).getMachineBasicBlock();
       return false;
@@ -331,7 +337,7 @@
   
   // If there are three terminators, we don't know what sort of block this is.
   if (SecondLastInst && I != MBB.begin() &&
-      isTerminatorInstr((--I)->getOpcode()))
+      !isPredicated(--I) && isTerminatorInstr(I->getOpcode()))
     return true;
   
   // If the block ends with ARM::B/ARM::tB and a ARM::Bcc/ARM::tBcc, handle it.
@@ -407,6 +413,11 @@
   if (MBB.empty()) return false;
   
   switch (MBB.back().getOpcode()) {
+  case ARM::BX_RET:   // Return.
+  case ARM::LDM_RET:
+  case ARM::tBX_RET:
+  case ARM::tBX_RET_vararg:
+  case ARM::tPOP_RET:
   case ARM::B:
   case ARM::tB:       // Uncond branch.
   case ARM::tBR_JTr: