[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

[Dale Johannesen]

Changes in directory llvm/lib/CodeGen/SelectionDAG:

DAGCombiner.cpp updated: 1.306 -> 1.307
---
Log message:

Don't fold bitconvert(load) for preinc/postdec loads.  Likewise stores.


---
Diffs of the changes:  (+3 -1)

 DAGCombiner.cpp |    4 +++-
 1 files changed, 3 insertions(+), 1 deletion(-)


Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.306 llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.307
--- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.306	Wed May 16 01:37:59 2007
+++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp	Wed May 16 17:45:30 2007
@@ -2685,6 +2685,7 @@
   // fold (conv (load x)) -> (load (conv*)x)
   // If the resultant load doesn't need a  higher alignment than the original!
   if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() &&
+      ISD::isUNINDEXEDLoad(N0.Val) &&
       TLI.isOperationLegal(ISD::LOAD, VT)) {
     LoadSDNode *LN0 = cast<LoadSDNode>(N0);
     unsigned Align = TLI.getTargetMachine().getTargetData()->
@@ -3563,7 +3564,8 @@
   
   // If this is a store of a bit convert, store the input value if the
   // resultant store does not need a higher alignment than the original.
-  if (Value.getOpcode() == ISD::BIT_CONVERT && !ST->isTruncatingStore()) {
+  if (Value.getOpcode() == ISD::BIT_CONVERT && !ST->isTruncatingStore() &&
+      ST->getAddressingMode() == ISD::UNINDEXED) {
     unsigned Align = ST->getAlignment();
     MVT::ValueType SVT = Value.getOperand(0).getValueType();
     unsigned OrigAlign = TLI.getTargetMachine().getTargetData()->