[llvm-commits] CVS: llvm/lib/Target/ARM/ARMInstrInfo.cpp ARMInstrInfo.h ARMTargetMachine.cpp ARMTargetMachine.h

[Evan Cheng]

On May 15, 2007, at 11:50 PM, Chris Lattner wrote:

>> Hooks for predication support.
>
> yay!
>
>> +bool ARMInstrInfo::isPredicatable(MachineInstr *MI) const {
>> +  const TargetInstrDescriptor *TID = MI->getInstrDescriptor();
>> +  if (TID->Flags & M_PREDICATED)
>> +    return true;
>> +
>> +  unsigned Opc = MI->getOpcode();
>> +  return Opc == ARM::B || Opc == ARM::tB;
>> +}
>> +
>> +void ARMInstrInfo::PredicateInstruction(MachineInstr *MI,
>> +                                      std::vector<MachineOperand>
>> &Cond) const {
>> +  unsigned Opc = MI->getOpcode();
>> +  if (Opc == ARM::B || Opc == ARM::tB) {
>> +    MI->setInstrDescriptor(get(Opc == ARM::B ? ARM::Bcc :
>> ARM::tBcc));
>> +    MI->addImmOperand(Cond[0].getImmedValue());
>> +    return;
>> +  }
>> +
>> +  MachineOperand *PMO = MI->findFirstPredOperand();
>> +  PMO->setImm(Cond[0].getImmedValue());
>> +}
>
> I don't think there is any reason for this to be virtual and target-
> specific.  In particular, can you please model B/tB the same way PPC
> handles branches (where an uncond branch is just a conditional branch
> where the condition is set to 'always')?  That way, you don't need a
> special case, isPredicatable doesn't need to be virtual, and each
> target doesn't need to implement PredicateInstruction.

Hrm? PPC has two separate opcodes for conditional and unconditional  
branches.

Are you talking about not having separate opcodes representing  
conditional and unconditional branches? I suppose that's ok except  
for some additional complexity added to AnalyzeBranch (and the fact  
it's harder to read the debug output). I'd prefer to keep the two  
separate (but ok with giving ARM::B a ''always' predicate).

But even then I am not sure if that eliminate the need to have a  
virtual function isPredicatable. Conditional branches probably would  
require special handling. Also, while it isn't possible now, it's  
conceivable some instruction predicate field may not be 'always'  
coming into the if-conversion pass. In that case, it would require a  
target hook to examine the field anyway.

Evan

>
> -Chris
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