[llvm-commits] CVS: llvm/lib/Target/ARM/ARMAsmPrinter.cpp ARMInstrInfo.td ARMInstrThumb.td ARMInstrVFP.td

Evan Cheng evan.cheng at apple.com
Tue May 8 14:09:01 PDT 2007



Changes in directory llvm/lib/Target/ARM:

ARMAsmPrinter.cpp updated: 1.72 -> 1.73
ARMInstrInfo.td updated: 1.99 -> 1.100
ARMInstrThumb.td updated: 1.25 -> 1.26
ARMInstrVFP.td updated: 1.4 -> 1.5
---
Log message:

Switch BCC, MOVCCr, etc. to PredicateOperand.

---
Diffs of the changes:  (+22 -17)

 ARMAsmPrinter.cpp |    4 ++--
 ARMInstrInfo.td   |   23 ++++++++++++++---------
 ARMInstrThumb.td  |    4 ++--
 ARMInstrVFP.td    |    8 ++++----
 4 files changed, 22 insertions(+), 17 deletions(-)


Index: llvm/lib/Target/ARM/ARMAsmPrinter.cpp
diff -u llvm/lib/Target/ARM/ARMAsmPrinter.cpp:1.72 llvm/lib/Target/ARM/ARMAsmPrinter.cpp:1.73
--- llvm/lib/Target/ARM/ARMAsmPrinter.cpp:1.72	Thu May  3 18:30:36 2007
+++ llvm/lib/Target/ARM/ARMAsmPrinter.cpp	Tue May  8 16:08:43 2007
@@ -101,7 +101,7 @@
     void printThumbAddrModeS2Operand(const MachineInstr *MI, int OpNo);
     void printThumbAddrModeS4Operand(const MachineInstr *MI, int OpNo);
     void printThumbAddrModeSPOperand(const MachineInstr *MI, int OpNo);
-    void printCCOperand(const MachineInstr *MI, int opNum);
+    void printPredicateOperand(const MachineInstr *MI, int opNum);
     void printPCLabel(const MachineInstr *MI, int opNum);
     void printRegisterList(const MachineInstr *MI, int opNum);
     void printCPInstOperand(const MachineInstr *MI, int opNum,
@@ -613,7 +613,7 @@
   O << "]";
 }
 
-void ARMAsmPrinter::printCCOperand(const MachineInstr *MI, int opNum) {
+void ARMAsmPrinter::printPredicateOperand(const MachineInstr *MI, int opNum) {
   int CC = (int)MI->getOperand(opNum).getImmedValue();
   O << ARMCondCodeToString((ARMCC::CondCodes)CC);
 }


Index: llvm/lib/Target/ARM/ARMInstrInfo.td
diff -u llvm/lib/Target/ARM/ARMInstrInfo.td:1.99 llvm/lib/Target/ARM/ARMInstrInfo.td:1.100
--- llvm/lib/Target/ARM/ARMInstrInfo.td:1.99	Fri Apr 27 19:36:37 2007
+++ llvm/lib/Target/ARM/ARMInstrInfo.td	Tue May  8 16:08:43 2007
@@ -162,11 +162,6 @@
 // Branch target.
 def brtarget : Operand<OtherVT>;
 
-// Operand for printing out a condition code.
-def CCOp : Operand<i32> {
-  let PrintMethod = "printCCOperand";
-}
-
 // A list of registers separated by comma. Used by load/store multiple.
 def reglist : Operand<i32> {
   let PrintMethod = "printRegisterList";
@@ -282,6 +277,16 @@
   let MIOperandInfo = (ops GPR, i32imm);
 }
 
+// ARM branch / cmov condition code operand.
+def ccop : PredicateOperand<i32, (ops i32imm), (ops)> {
+  let PrintMethod = "printPredicateOperand";
+}
+
+// ARM Predicate operand. Default to 14 = always (AL).
+def pred : PredicateOperand<i32, (ops i32imm), (ops (i32 14))> {
+  let PrintMethod = "printPredicateOperand";
+}
+
 //===----------------------------------------------------------------------===//
 // ARM Instruction flags.  These need to match ARMInstrInfo.h.
 //
@@ -579,7 +584,7 @@
 }
 
 let isBranch = 1, isTerminator = 1, noResults = 1, isBarrier = 1 in
-  def Bcc : AI<(ops brtarget:$dst, CCOp:$cc), "b$cc $dst",
+  def Bcc : AI<(ops brtarget:$dst, ccop:$cc), "b$cc $dst",
                 [(ARMbrcond bb:$dst, imm:$cc)]>;
 
 //===----------------------------------------------------------------------===//
@@ -1041,17 +1046,17 @@
 
 
 // Conditional moves
-def MOVCCr : AI<(ops GPR:$dst, GPR:$false, GPR:$true, CCOp:$cc),
+def MOVCCr : AI<(ops GPR:$dst, GPR:$false, GPR:$true, ccop:$cc),
                 "mov$cc $dst, $true",
                 [(set GPR:$dst, (ARMcmov GPR:$false, GPR:$true, imm:$cc))]>,
                 RegConstraint<"$false = $dst">;
 
-def MOVCCs : AI<(ops GPR:$dst, GPR:$false, so_reg:$true, CCOp:$cc),
+def MOVCCs : AI<(ops GPR:$dst, GPR:$false, so_reg:$true, ccop:$cc),
                 "mov$cc $dst, $true",
                 [(set GPR:$dst, (ARMcmov GPR:$false, so_reg:$true,imm:$cc))]>,
                 RegConstraint<"$false = $dst">;
 
-def MOVCCi : AI<(ops GPR:$dst, GPR:$false, so_imm:$true, CCOp:$cc),
+def MOVCCi : AI<(ops GPR:$dst, GPR:$false, so_imm:$true, ccop:$cc),
                 "mov$cc $dst, $true",
                 [(set GPR:$dst, (ARMcmov GPR:$false, so_imm:$true,imm:$cc))]>,
                 RegConstraint<"$false = $dst">;


Index: llvm/lib/Target/ARM/ARMInstrThumb.td
diff -u llvm/lib/Target/ARM/ARMInstrThumb.td:1.25 llvm/lib/Target/ARM/ARMInstrThumb.td:1.26
--- llvm/lib/Target/ARM/ARMInstrThumb.td:1.25	Tue May  1 15:27:19 2007
+++ llvm/lib/Target/ARM/ARMInstrThumb.td	Tue May  8 16:08:43 2007
@@ -207,7 +207,7 @@
 }
 
 let isBranch = 1, isTerminator = 1, noResults = 1, isBarrier = 1 in
-  def tBcc : TI<(ops brtarget:$dst, CCOp:$cc), "b$cc $dst",
+  def tBcc : TI<(ops brtarget:$dst, ccop:$cc), "b$cc $dst",
                  [(ARMbrcond bb:$dst, imm:$cc)]>;
 
 //===----------------------------------------------------------------------===//
@@ -503,7 +503,7 @@
 // Expanded by the scheduler into a branch sequence.
 let usesCustomDAGSchedInserter = 1 in  // Expanded by the scheduler.
   def tMOVCCr :
-  PseudoInst<(ops GPR:$dst, GPR:$false, GPR:$true, CCOp:$cc),
+  PseudoInst<(ops GPR:$dst, GPR:$false, GPR:$true, ccop:$cc),
               "@ tMOVCCr $cc",
               [(set GPR:$dst, (ARMcmov GPR:$false, GPR:$true, imm:$cc))]>;
 


Index: llvm/lib/Target/ARM/ARMInstrVFP.td
diff -u llvm/lib/Target/ARM/ARMInstrVFP.td:1.4 llvm/lib/Target/ARM/ARMInstrVFP.td:1.5
--- llvm/lib/Target/ARM/ARMInstrVFP.td:1.4	Mon May  7 16:29:41 2007
+++ llvm/lib/Target/ARM/ARMInstrVFP.td	Tue May  8 16:08:43 2007
@@ -344,22 +344,22 @@
 // FP Conditional moves.
 //
 
-def FCPYDcc  : ADI<(ops DPR:$dst, DPR:$false, DPR:$true, CCOp:$cc),
+def FCPYDcc  : ADI<(ops DPR:$dst, DPR:$false, DPR:$true, ccop:$cc),
                    "fcpyd$cc $dst, $true",
                    [(set DPR:$dst, (ARMcmov DPR:$false, DPR:$true, imm:$cc))]>,
                    RegConstraint<"$false = $dst">;
 
-def FCPYScc  : ASI<(ops SPR:$dst, SPR:$false, SPR:$true, CCOp:$cc),
+def FCPYScc  : ASI<(ops SPR:$dst, SPR:$false, SPR:$true, ccop:$cc),
                    "fcpys$cc $dst, $true",
                    [(set SPR:$dst, (ARMcmov SPR:$false, SPR:$true, imm:$cc))]>,
                    RegConstraint<"$false = $dst">;
 
-def FNEGDcc  : ADI<(ops DPR:$dst, DPR:$false, DPR:$true, CCOp:$cc),
+def FNEGDcc  : ADI<(ops DPR:$dst, DPR:$false, DPR:$true, ccop:$cc),
                    "fnegd$cc $dst, $true",
                    [(set DPR:$dst, (ARMcneg DPR:$false, DPR:$true, imm:$cc))]>,
                    RegConstraint<"$false = $dst">;
 
-def FNEGScc  : ASI<(ops SPR:$dst, SPR:$false, SPR:$true, CCOp:$cc),
+def FNEGScc  : ASI<(ops SPR:$dst, SPR:$false, SPR:$true, ccop:$cc),
                    "fnegs$cc $dst, $true",
                    [(set SPR:$dst, (ARMcneg SPR:$false, SPR:$true, imm:$cc))]>,
                    RegConstraint<"$false = $dst">;






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