[llvm-commits] CVS: llvm/lib/CodeGen/RegAllocLinearScan.cpp RegAllocLocal.cpp

Bill Wendling isanbard at gmail.com
Tue May 8 12:03:04 PDT 2007



Changes in directory llvm/lib/CodeGen:

RegAllocLinearScan.cpp updated: 1.148 -> 1.149
RegAllocLocal.cpp updated: 1.105 -> 1.106
---
Log message:

Change names from RA to something unique to get rid of naming conflicts with
certain linkers...


---
Diffs of the changes:  (+42 -38)

 RegAllocLinearScan.cpp |   36 +++++++++++++++++++-----------------
 RegAllocLocal.cpp      |   44 +++++++++++++++++++++++---------------------
 2 files changed, 42 insertions(+), 38 deletions(-)


Index: llvm/lib/CodeGen/RegAllocLinearScan.cpp
diff -u llvm/lib/CodeGen/RegAllocLinearScan.cpp:1.148 llvm/lib/CodeGen/RegAllocLinearScan.cpp:1.149
--- llvm/lib/CodeGen/RegAllocLinearScan.cpp:1.148	Wed May  2 20:11:53 2007
+++ llvm/lib/CodeGen/RegAllocLinearScan.cpp	Tue May  8 14:02:46 2007
@@ -47,9 +47,9 @@
   static unsigned numIterations = 0;
   static unsigned numIntervals = 0;
 
-  struct VISIBILITY_HIDDEN RA : public MachineFunctionPass {
+  struct VISIBILITY_HIDDEN RALinScan : public MachineFunctionPass {
     static char ID;
-    RA() : MachineFunctionPass((intptr_t)&ID) {}
+    RALinScan() : MachineFunctionPass((intptr_t)&ID) {}
 
     typedef std::pair<LiveInterval*, LiveInterval::iterator> IntervalPtr;
     typedef std::vector<IntervalPtr> IntervalPtrs;
@@ -149,10 +149,10 @@
       }
     }
   };
-  char RA::ID = 0;
+  char RALinScan::ID = 0;
 }
 
-void RA::ComputeRelatedRegClasses() {
+void RALinScan::ComputeRelatedRegClasses() {
   const MRegisterInfo &MRI = *mri_;
   
   // First pass, add all reg classes to the union, and determine at least one
@@ -187,7 +187,7 @@
         RelatedRegClasses.unionSets(I->second, OneClassForEachPhysReg[*AS]);
 }
 
-bool RA::runOnMachineFunction(MachineFunction &fn) {
+bool RALinScan::runOnMachineFunction(MachineFunction &fn) {
   mf_ = &fn;
   tm_ = &fn.getTarget();
   mri_ = tm_->getRegisterInfo();
@@ -222,7 +222,7 @@
 
 /// initIntervalSets - initialize the interval sets.
 ///
-void RA::initIntervalSets()
+void RALinScan::initIntervalSets()
 {
   assert(unhandled_.empty() && fixed_.empty() &&
          active_.empty() && inactive_.empty() &&
@@ -237,7 +237,7 @@
   }
 }
 
-void RA::linearScan()
+void RALinScan::linearScan()
 {
   // linear scan algorithm
   DOUT << "********** LINEAR SCAN **********\n";
@@ -317,7 +317,7 @@
 
 /// processActiveIntervals - expire old intervals and move non-overlapping ones
 /// to the inactive list.
-void RA::processActiveIntervals(unsigned CurPoint)
+void RALinScan::processActiveIntervals(unsigned CurPoint)
 {
   DOUT << "\tprocessing active intervals:\n";
 
@@ -363,7 +363,7 @@
 
 /// processInactiveIntervals - expire old intervals and move overlapping
 /// ones to the active list.
-void RA::processInactiveIntervals(unsigned CurPoint)
+void RALinScan::processInactiveIntervals(unsigned CurPoint)
 {
   DOUT << "\tprocessing inactive intervals:\n";
 
@@ -412,16 +412,18 @@
     Weights[*as] += weight;
 }
 
-static RA::IntervalPtrs::iterator FindIntervalInVector(RA::IntervalPtrs &IP,
-                                                       LiveInterval *LI) {
-  for (RA::IntervalPtrs::iterator I = IP.begin(), E = IP.end(); I != E; ++I)
+static
+RALinScan::IntervalPtrs::iterator
+FindIntervalInVector(RALinScan::IntervalPtrs &IP, LiveInterval *LI) {
+  for (RALinScan::IntervalPtrs::iterator I = IP.begin(), E = IP.end();
+       I != E; ++I)
     if (I->first == LI) return I;
   return IP.end();
 }
 
-static void RevertVectorIteratorsTo(RA::IntervalPtrs &V, unsigned Point) {
+static void RevertVectorIteratorsTo(RALinScan::IntervalPtrs &V, unsigned Point){
   for (unsigned i = 0, e = V.size(); i != e; ++i) {
-    RA::IntervalPtr &IP = V[i];
+    RALinScan::IntervalPtr &IP = V[i];
     LiveInterval::iterator I = std::upper_bound(IP.first->begin(),
                                                 IP.second, Point);
     if (I != IP.first->begin()) --I;
@@ -431,7 +433,7 @@
 
 /// assignRegOrStackSlotAtInterval - assign a register if one is available, or
 /// spill.
-void RA::assignRegOrStackSlotAtInterval(LiveInterval* cur)
+void RALinScan::assignRegOrStackSlotAtInterval(LiveInterval* cur)
 {
   DOUT << "\tallocating current interval: ";
 
@@ -752,7 +754,7 @@
 
 /// getFreePhysReg - return a free physical register for this virtual register
 /// interval if we have one, otherwise return 0.
-unsigned RA::getFreePhysReg(LiveInterval *cur) {
+unsigned RALinScan::getFreePhysReg(LiveInterval *cur) {
   std::vector<unsigned> inactiveCounts(mri_->getNumRegs(), 0);
   unsigned MaxInactiveCount = 0;
   
@@ -821,5 +823,5 @@
 }
 
 FunctionPass* llvm::createLinearScanRegisterAllocator() {
-  return new RA();
+  return new RALinScan();
 }


Index: llvm/lib/CodeGen/RegAllocLocal.cpp
diff -u llvm/lib/CodeGen/RegAllocLocal.cpp:1.105 llvm/lib/CodeGen/RegAllocLocal.cpp:1.106
--- llvm/lib/CodeGen/RegAllocLocal.cpp:1.105	Wed May  2 20:11:53 2007
+++ llvm/lib/CodeGen/RegAllocLocal.cpp	Tue May  8 14:02:46 2007
@@ -42,10 +42,10 @@
                   createLocalRegisterAllocator);
 
 
-  class VISIBILITY_HIDDEN RA : public MachineFunctionPass {
+  class VISIBILITY_HIDDEN RALocal : public MachineFunctionPass {
   public:
     static char ID;
-    RA() : MachineFunctionPass((intptr_t)&ID) {}
+    RALocal() : MachineFunctionPass((intptr_t)&ID) {}
   private:
     const TargetMachine *TM;
     MachineFunction *MF;
@@ -228,12 +228,12 @@
     void reloadPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator &I,
                        unsigned PhysReg);
   };
-  char RA::ID = 0;
+  char RALocal::ID = 0;
 }
 
 /// getStackSpaceFor - This allocates space for the specified virtual register
 /// to be held on the stack.
-int RA::getStackSpaceFor(unsigned VirtReg, const TargetRegisterClass *RC) {
+int RALocal::getStackSpaceFor(unsigned VirtReg, const TargetRegisterClass *RC) {
   // Find the location Reg would belong...
   std::map<unsigned, int>::iterator I =StackSlotForVirtReg.lower_bound(VirtReg);
 
@@ -253,7 +253,7 @@
 /// removePhysReg - This method marks the specified physical register as no
 /// longer being in use.
 ///
-void RA::removePhysReg(unsigned PhysReg) {
+void RALocal::removePhysReg(unsigned PhysReg) {
   PhysRegsUsed[PhysReg] = -1;      // PhyReg no longer used
 
   std::vector<unsigned>::iterator It =
@@ -267,8 +267,9 @@
 /// virtual register slot specified by VirtReg.  It then updates the RA data
 /// structures to indicate the fact that PhysReg is now available.
 ///
-void RA::spillVirtReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
-                      unsigned VirtReg, unsigned PhysReg) {
+void RALocal::spillVirtReg(MachineBasicBlock &MBB,
+                           MachineBasicBlock::iterator I,
+                           unsigned VirtReg, unsigned PhysReg) {
   assert(VirtReg && "Spilling a physical register is illegal!"
          " Must not have appropriate kill for the register or use exists beyond"
          " the intended one.");
@@ -300,8 +301,8 @@
 /// then the request is ignored if the physical register does not contain a
 /// virtual register.
 ///
-void RA::spillPhysReg(MachineBasicBlock &MBB, MachineInstr *I,
-                      unsigned PhysReg, bool OnlyVirtRegs) {
+void RALocal::spillPhysReg(MachineBasicBlock &MBB, MachineInstr *I,
+                           unsigned PhysReg, bool OnlyVirtRegs) {
   if (PhysRegsUsed[PhysReg] != -1) {            // Only spill it if it's used!
     assert(PhysRegsUsed[PhysReg] != -2 && "Non allocable reg used!");
     if (PhysRegsUsed[PhysReg] || !OnlyVirtRegs)
@@ -334,7 +335,7 @@
 /// that PhysReg is the proper container for VirtReg now.  The physical
 /// register must not be used for anything else when this is called.
 ///
-void RA::assignVirtToPhysReg(unsigned VirtReg, unsigned PhysReg) {
+void RALocal::assignVirtToPhysReg(unsigned VirtReg, unsigned PhysReg) {
   assert(PhysRegsUsed[PhysReg] == -1 && "Phys reg already assigned!");
   // Update information to note the fact that this register was just used, and
   // it holds VirtReg.
@@ -348,7 +349,7 @@
 /// and available for use.  This also includes checking to see if aliased
 /// registers are all free...
 ///
-bool RA::isPhysRegAvailable(unsigned PhysReg) const {
+bool RALocal::isPhysRegAvailable(unsigned PhysReg) const {
   if (PhysRegsUsed[PhysReg] != -1) return false;
 
   // If the selected register aliases any other allocated registers, it is
@@ -364,7 +365,7 @@
 /// getFreeReg - Look to see if there is a free register available in the
 /// specified register class.  If not, return 0.
 ///
-unsigned RA::getFreeReg(const TargetRegisterClass *RC) {
+unsigned RALocal::getFreeReg(const TargetRegisterClass *RC) {
   // Get iterators defining the range of registers that are valid to allocate in
   // this class, which also specifies the preferred allocation order.
   TargetRegisterClass::iterator RI = RC->allocation_order_begin(*MF);
@@ -383,8 +384,9 @@
 /// use.  If there is currently a value in it, it is either moved out of the way
 /// or spilled to memory.
 ///
-void RA::liberatePhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator &I,
-                         unsigned PhysReg) {
+void RALocal::liberatePhysReg(MachineBasicBlock &MBB,
+                              MachineBasicBlock::iterator &I,
+                              unsigned PhysReg) {
   spillPhysReg(MBB, I, PhysReg);
 }
 
@@ -393,8 +395,8 @@
 /// register.  If all compatible physical registers are used, this method spills
 /// the last used virtual register to the stack, and uses that register.
 ///
-unsigned RA::getReg(MachineBasicBlock &MBB, MachineInstr *I,
-                    unsigned VirtReg) {
+unsigned RALocal::getReg(MachineBasicBlock &MBB, MachineInstr *I,
+                         unsigned VirtReg) {
   const TargetRegisterClass *RC = MF->getSSARegMap()->getRegClass(VirtReg);
 
   // First check to see if we have a free register of the requested type...
@@ -470,8 +472,8 @@
 /// subsequent instructions can use the reloaded value.  This method returns the
 /// modified instruction.
 ///
-MachineInstr *RA::reloadVirtReg(MachineBasicBlock &MBB, MachineInstr *MI,
-                                unsigned OpNum) {
+MachineInstr *RALocal::reloadVirtReg(MachineBasicBlock &MBB, MachineInstr *MI,
+                                     unsigned OpNum) {
   unsigned VirtReg = MI->getOperand(OpNum).getReg();
 
   // If the virtual register is already available, just update the instruction
@@ -522,7 +524,7 @@
 
 
 
-void RA::AllocateBasicBlock(MachineBasicBlock &MBB) {
+void RALocal::AllocateBasicBlock(MachineBasicBlock &MBB) {
   // loop over each instruction
   MachineBasicBlock::iterator MII = MBB.begin();
   const TargetInstrInfo &TII = *TM->getInstrInfo();
@@ -776,7 +778,7 @@
 
 /// runOnMachineFunction - Register allocate the whole function
 ///
-bool RA::runOnMachineFunction(MachineFunction &Fn) {
+bool RALocal::runOnMachineFunction(MachineFunction &Fn) {
   DOUT << "Machine Function " << "\n";
   MF = &Fn;
   TM = &Fn.getTarget();
@@ -812,5 +814,5 @@
 }
 
 FunctionPass *llvm::createLocalRegisterAllocator() {
-  return new RA();
+  return new RALocal();
 }






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