[llvm-commits] CVS: llvm/lib/Target/ARM/ARMInstrThumb.td

[Evan Cheng]

Changes in directory llvm/lib/Target/ARM:

ARMInstrThumb.td updated: 1.22 -> 1.23
---
Log message:

Back out previous check-in. Incorrect.

---
Diffs of the changes:  (+2 -6)

 ARMInstrThumb.td |    8 ++------
 1 files changed, 2 insertions(+), 6 deletions(-)


Index: llvm/lib/Target/ARM/ARMInstrThumb.td
diff -u llvm/lib/Target/ARM/ARMInstrThumb.td:1.22 llvm/lib/Target/ARM/ARMInstrThumb.td:1.23
--- llvm/lib/Target/ARM/ARMInstrThumb.td:1.22	Fri Apr 27 02:37:22 2007
+++ llvm/lib/Target/ARM/ARMInstrThumb.td	Fri Apr 27 02:50:02 2007
@@ -56,10 +56,6 @@
 class TIx2<dag ops, string asm, list<dag> pattern>
   : ThumbI<ops, AddrModeNone, Size4Bytes, asm, "", pattern>;
 
-// tLEApcrel and tLEApcrelJT
-class TIsx2<dag ops, string asm, list<dag> pattern>
-  : ThumbI<ops, AddrModeTs, Size4Bytes, asm, "", pattern>;
-
 // BR_JT instructions
 class TJTI<dag ops, string asm, list<dag> pattern>
   : ThumbI<ops, AddrModeNone, SizeSpecial, asm, "", pattern>;
@@ -513,14 +509,14 @@
 
 // tLEApcrel - Load a pc-relative address into a register without offending the
 // assembler.
-def tLEApcrel : TIsx2<(ops GPR:$dst, i32imm:$label),
+def tLEApcrel : TIx2<(ops GPR:$dst, i32imm:$label),
                     !strconcat(!strconcat(".set PCRELV${:uid}, ($label-(",
                                           "${:private}PCRELL${:uid}+6))\n"),
                                !strconcat("\tmov $dst, #PCRELV${:uid}\n",
                                   "${:private}PCRELL${:uid}:\n\tadd $dst, pc")),
                     []>;
 
-def tLEApcrelJT : TIsx2<(ops GPR:$dst, i32imm:$label, i32imm:$id),
+def tLEApcrelJT : TIx2<(ops GPR:$dst, i32imm:$label, i32imm:$id),
           !strconcat(!strconcat(".set PCRELV${:uid}, (${label}_${id:no_hash}-(",
                                          "${:private}PCRELL${:uid}+4))\n"),
                      !strconcat("\tmov $dst, #PCRELV${:uid}\n",