[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp

[Bill Wendling]

Changes in directory llvm/lib/CodeGen/SelectionDAG:

SelectionDAGISel.cpp updated: 1.425 -> 1.426
---
Log message:

Assertion when using a 1-element vector for an add operation. Get the 
real vector type in this case.


---
Diffs of the changes:  (+7 -4)

 SelectionDAGISel.cpp |   11 +++++++----
 1 files changed, 7 insertions(+), 4 deletions(-)


Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.425 llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.426
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.425	Mon Apr 23 20:24:20 2007
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp	Tue Apr 24 16:13:23 2007
@@ -308,19 +308,22 @@
     const VectorType *PTy = cast<VectorType>(V->getType());
     unsigned NumElts = PTy->getNumElements();
     MVT::ValueType EltTy = TLI.getValueType(PTy->getElementType());
+    MVT::ValueType VecTy = getVectorType(EltTy, NumElts);
     
     // Divide the input until we get to a supported size.  This will always
     // end with a scalar if the target doesn't support vectors.
-    while (NumElts > 1 && !TLI.isTypeLegal(getVectorType(EltTy, NumElts))) {
+    while (NumElts > 1 && !TLI.isTypeLegal(VecTy)) {
       NumElts >>= 1;
       NumVectorRegs <<= 1;
     }
-    if (NumElts == 1)
+
+    // Check that VecTy isn't a 1-element vector.
+    if (NumElts == 1 && VecTy == MVT::Other)
       VT = EltTy;
     else
-      VT = getVectorType(EltTy, NumElts);
+      VT = VecTy;
   }
-  
+
   // The common case is that we will only create one register for this
   // value.  If we have that case, create and return the virtual register.
   unsigned NV = TLI.getNumElements(VT);