[llvm-commits] CVS: llvm/lib/Target/ARM/ARMRegisterInfo.td

[Evan Cheng]

Changes in directory llvm/lib/Target/ARM:

ARMRegisterInfo.td updated: 1.15 -> 1.16
---
Log message:

Specify S registers as D registers' sub-registers.

---
Diffs of the changes:  (+2 -2)

 ARMRegisterInfo.td |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)


Index: llvm/lib/Target/ARM/ARMRegisterInfo.td
diff -u llvm/lib/Target/ARM/ARMRegisterInfo.td:1.15 llvm/lib/Target/ARM/ARMRegisterInfo.td:1.16
--- llvm/lib/Target/ARM/ARMRegisterInfo.td:1.15	Wed Mar  7 20:56:40 2007
+++ llvm/lib/Target/ARM/ARMRegisterInfo.td	Fri Apr 20 16:20:10 2007
@@ -13,10 +13,10 @@
 //===----------------------------------------------------------------------===//
 
 // Registers are identified with 4-bit ID numbers.
-class ARMReg<bits<4> num, string n, list<Register> aliases = []> : Register<n> {
+class ARMReg<bits<4> num, string n, list<Register> subregs = []> : Register<n> {
   field bits<4> Num;
   let Namespace = "ARM";
-  let Aliases = aliases;
+  let SubRegs = subregs;
 }
 
 class ARMFReg<bits<5> num, string n> : Register<n> {