[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

[Chris Lattner]

Changes in directory llvm/lib/CodeGen/SelectionDAG:

DAGCombiner.cpp updated: 1.290 -> 1.291
---
Log message:

SIGN_EXTEND_INREG does not demand its top bits.  Give SimplifyDemandedBits
a chance to hack on it.  This compiles:

int baz(long long a) { return (short)(((int)(a >>24)) >> 9); }

into:
_baz:
        slwi r2, r3, 8
        srwi r2, r2, 9
        extsh r3, r2
        blr 

instead of:

_baz:
        srwi r2, r4, 24
        rlwimi r2, r3, 8, 0, 23
        srwi r2, r2, 9
        extsh r3, r2
        blr 

This implements CodeGen/PowerPC/sign_ext_inreg1.ll



---
Diffs of the changes:  (+6 -1)

 DAGCombiner.cpp |    7 ++++++-
 1 files changed, 6 insertions(+), 1 deletion(-)


Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.290 llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.291
--- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.290	Wed Apr 11 11:51:53 2007
+++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp	Tue Apr 17 14:03:21 2007
@@ -2429,10 +2429,15 @@
     return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0), N1);
   }
 
-  // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is zero
+  // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is known zero.
   if (TLI.MaskedValueIsZero(N0, 1ULL << (EVTBits-1)))
     return DAG.getZeroExtendInReg(N0, EVT);
   
+  // fold operands of sext_in_reg based on knowledge that the top bits are not
+  // demanded.
+  if (SimplifyDemandedBits(SDOperand(N, 0)))
+    return SDOperand(N, 0);
+  
   // fold (sext_in_reg (load x)) -> (smaller sextload x)
   // fold (sext_in_reg (srl (load x), c)) -> (smaller sextload (x+c/evtbits))
   SDOperand NarrowLoad = ReduceLoadWidth(N);