[llvm-commits] CVS: llvm/lib/Target/IA64/IA64Bundling.cpp IA64ISelDAGToDAG.cpp IA64ISelLowering.cpp
Anton Korobeynikov
asl at math.spbu.ru
Mon Apr 16 11:11:40 PDT 2007
Changes in directory llvm/lib/Target/IA64:
IA64Bundling.cpp updated: 1.7 -> 1.8
IA64ISelDAGToDAG.cpp updated: 1.64 -> 1.65
IA64ISelLowering.cpp updated: 1.56 -> 1.57
---
Log message:
Removed tabs everywhere except autogenerated & external files. Add make
target for tabs checking.
---
Diffs of the changes: (+39 -31)
IA64Bundling.cpp | 8 +++----
IA64ISelDAGToDAG.cpp | 52 +++++++++++++++++++++++++++++----------------------
IA64ISelLowering.cpp | 10 ++++-----
3 files changed, 39 insertions(+), 31 deletions(-)
Index: llvm/lib/Target/IA64/IA64Bundling.cpp
diff -u llvm/lib/Target/IA64/IA64Bundling.cpp:1.7 llvm/lib/Target/IA64/IA64Bundling.cpp:1.8
--- llvm/lib/Target/IA64/IA64Bundling.cpp:1.7 Tue Dec 19 16:59:26 2006
+++ llvm/lib/Target/IA64/IA64Bundling.cpp Mon Apr 16 13:10:23 2007
@@ -56,10 +56,10 @@
return Changed;
}
- std::set<unsigned> PendingRegWrites; // XXX: ugly global, but
- // pending writes can cross basic blocks. Note that
- // taken branches end instruction groups. So we
- // only need to worry about 'fallthrough' code
+ // XXX: ugly global, but pending writes can cross basic blocks. Note that
+ // taken branches end instruction groups. So we only need to worry about
+ // 'fallthrough' code
+ std::set<unsigned> PendingRegWrites;
};
} // end of anonymous namespace
Index: llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp
diff -u llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.64 llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.65
--- llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp:1.64 Tue Dec 19 16:59:26 2006
+++ llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp Mon Apr 16 13:10:23 2007
@@ -352,9 +352,10 @@
Chain = targetEntryPoint.getValue(1);
SDOperand targetGPAddr=
SDOperand(CurDAG->getTargetNode(IA64::ADDS, MVT::i64,
- FnDescriptor, CurDAG->getConstant(8, MVT::i64)), 0);
+ FnDescriptor,
+ CurDAG->getConstant(8, MVT::i64)), 0);
Chain = targetGPAddr.getValue(1);
- SDOperand targetGP=
+ SDOperand targetGP =
SDOperand(CurDAG->getTargetNode(IA64::LD8, MVT::i64, targetGPAddr), 0);
Chain = targetGP.getValue(1);
@@ -418,14 +419,14 @@
int FI = cast<FrameIndexSDNode>(N)->getIndex();
if (N->hasOneUse())
return CurDAG->SelectNodeTo(N, IA64::MOV, MVT::i64,
- CurDAG->getTargetFrameIndex(FI, MVT::i64));
+ CurDAG->getTargetFrameIndex(FI, MVT::i64));
else
return CurDAG->getTargetNode(IA64::MOV, MVT::i64,
CurDAG->getTargetFrameIndex(FI, MVT::i64));
}
case ISD::ConstantPool: { // TODO: nuke the constant pool
- // (ia64 doesn't need one)
+ // (ia64 doesn't need one)
ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(N);
Constant *C = CP->getConstVal();
SDOperand CPI = CurDAG->getTargetConstantPool(C, MVT::i64,
@@ -437,18 +438,24 @@
case ISD::GlobalAddress: {
GlobalValue *GV = cast<GlobalAddressSDNode>(N)->getGlobal();
SDOperand GA = CurDAG->getTargetGlobalAddress(GV, MVT::i64);
- SDOperand Tmp = SDOperand(CurDAG->getTargetNode(IA64::ADDL_GA, MVT::i64,
- CurDAG->getRegister(IA64::r1, MVT::i64), GA), 0);
+ SDOperand Tmp =
+ SDOperand(CurDAG->getTargetNode(IA64::ADDL_GA, MVT::i64,
+ CurDAG->getRegister(IA64::r1,
+ MVT::i64), GA), 0);
return CurDAG->getTargetNode(IA64::LD8, MVT::i64, Tmp);
}
-/* XXX case ISD::ExternalSymbol: {
- SDOperand EA = CurDAG->getTargetExternalSymbol(cast<ExternalSymbolSDNode>(N)->getSymbol(),
- MVT::i64);
- SDOperand Tmp = CurDAG->getTargetNode(IA64::ADDL_EA, MVT::i64,
- CurDAG->getRegister(IA64::r1, MVT::i64), EA);
- return CurDAG->getTargetNode(IA64::LD8, MVT::i64, Tmp);
- }
+/* XXX
+ case ISD::ExternalSymbol: {
+ SDOperand EA = CurDAG->getTargetExternalSymbol(
+ cast<ExternalSymbolSDNode>(N)->getSymbol(),
+ MVT::i64);
+ SDOperand Tmp = CurDAG->getTargetNode(IA64::ADDL_EA, MVT::i64,
+ CurDAG->getRegister(IA64::r1,
+ MVT::i64),
+ EA);
+ return CurDAG->getTargetNode(IA64::LD8, MVT::i64, Tmp);
+ }
*/
case ISD::LOAD: { // FIXME: load -1, not 1, for bools?
@@ -504,15 +511,16 @@
default: assert(0 && "unknown type in store");
case MVT::i1: { // this is a bool
Opc = IA64::ST1; // we store either 0 or 1 as a byte
- // first load zero!
- SDOperand Initial = CurDAG->getCopyFromReg(Chain, IA64::r0, MVT::i64);
- Chain = Initial.getValue(1);
- // then load 1 into the same reg iff the predicate to store is 1
+ // first load zero!
+ SDOperand Initial = CurDAG->getCopyFromReg(Chain, IA64::r0, MVT::i64);
+ Chain = Initial.getValue(1);
+ // then load 1 into the same reg iff the predicate to store is 1
SDOperand Tmp = ST->getValue();
AddToISelQueue(Tmp);
- Tmp = SDOperand(CurDAG->getTargetNode(IA64::TPCADDS, MVT::i64, Initial,
- CurDAG->getTargetConstant(1, MVT::i64),
- Tmp), 0);
+ Tmp =
+ SDOperand(CurDAG->getTargetNode(IA64::TPCADDS, MVT::i64, Initial,
+ CurDAG->getTargetConstant(1, MVT::i64),
+ Tmp), 0);
return CurDAG->SelectNodeTo(N, Opc, MVT::Other, Address, Tmp, Chain);
}
case MVT::i64: Opc = IA64::ST8; break;
@@ -551,14 +559,14 @@
case ISD::CALLSEQ_END: {
int64_t Amt = cast<ConstantSDNode>(N->getOperand(1))->getValue();
unsigned Opc = N->getOpcode() == ISD::CALLSEQ_START ?
- IA64::ADJUSTCALLSTACKDOWN : IA64::ADJUSTCALLSTACKUP;
+ IA64::ADJUSTCALLSTACKDOWN : IA64::ADJUSTCALLSTACKUP;
SDOperand N0 = N->getOperand(0);
AddToISelQueue(N0);
return CurDAG->SelectNodeTo(N, Opc, MVT::Other, getI64Imm(Amt), N0);
}
case ISD::BR:
- // FIXME: we don't need long branches all the time!
+ // FIXME: we don't need long branches all the time!
SDOperand N0 = N->getOperand(0);
AddToISelQueue(N0);
return CurDAG->SelectNodeTo(N, IA64::BRL_NOTCALL, MVT::Other,
Index: llvm/lib/Target/IA64/IA64ISelLowering.cpp
diff -u llvm/lib/Target/IA64/IA64ISelLowering.cpp:1.56 llvm/lib/Target/IA64/IA64ISelLowering.cpp:1.57
--- llvm/lib/Target/IA64/IA64ISelLowering.cpp:1.56 Wed Mar 7 10:25:09 2007
+++ llvm/lib/Target/IA64/IA64ISelLowering.cpp Mon Apr 16 13:10:23 2007
@@ -366,9 +366,9 @@
ValToStore = Val;
} else {
RegValuesToPass.push_back(Val);
- if(1 /* TODO: if(calling external or varadic function)*/ ) {
- ValToConvert = Val; // additionally pass this FP value as an int
- }
+ if(1 /* TODO: if(calling external or varadic function)*/ ) {
+ ValToConvert = Val; // additionally pass this FP value as an int
+ }
}
break;
}
@@ -384,7 +384,7 @@
}
if(ValToConvert.Val) {
- Converts.push_back(DAG.getNode(IA64ISD::GETFD, MVT::i64, ValToConvert));
+ Converts.push_back(DAG.getNode(IA64ISD::GETFD, MVT::i64, ValToConvert));
}
}
@@ -492,7 +492,7 @@
Chain = boolInR8.getValue(1);
SDOperand zeroReg = DAG.getCopyFromReg(Chain, IA64::r0, MVT::i64, InFlag);
InFlag = zeroReg.getValue(2);
- Chain = zeroReg.getValue(1);
+ Chain = zeroReg.getValue(1);
RetVal = DAG.getSetCC(MVT::i1, boolInR8, zeroReg, ISD::SETNE);
break;
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