[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp

[Chris Lattner]

Changes in directory llvm/lib/Target/X86:

X86ISelLowering.cpp updated: 1.383 -> 1.384
---
Log message:

implement CodeGen/X86/inline-asm-x-scalar.ll


---
Diffs of the changes:  (+15 -1)

 X86ISelLowering.cpp |   16 +++++++++++++++-
 1 files changed, 15 insertions(+), 1 deletion(-)


Index: llvm/lib/Target/X86/X86ISelLowering.cpp
diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.383 llvm/lib/Target/X86/X86ISelLowering.cpp:1.384
--- llvm/lib/Target/X86/X86ISelLowering.cpp:1.383	Fri Mar 30 18:15:24 2007
+++ llvm/lib/Target/X86/X86ISelLowering.cpp	Mon Apr  9 00:11:28 2007
@@ -4640,7 +4640,6 @@
   return TargetLowering::isOperandValidForConstraint(Op, Constraint, DAG);
 }
 
-
 std::vector<unsigned> X86TargetLowering::
 getRegClassForInlineAsmConstraint(const std::string &Constraint,
                                   MVT::ValueType VT) const {
@@ -4709,6 +4708,21 @@
 std::pair<unsigned, const TargetRegisterClass*>
 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
                                                 MVT::ValueType VT) const {
+  // First, see if this is a constraint that directly corresponds to an LLVM
+  // register class.
+  if (Constraint.size() == 1) {
+    // GCC Constraint Letters
+    switch (Constraint[0]) {
+    default: break;
+    case 'x': 
+      if (VT == MVT::f32)
+        return std::make_pair(0U, X86::FR32RegisterClass);
+      if (VT == MVT::f64)
+        return std::make_pair(0U, X86::FR64RegisterClass);
+      break;
+    }
+  }
+  
   // Use the default implementation in TargetLowering to convert the register
   // constraint into a member of a register class.
   std::pair<unsigned, const TargetRegisterClass*> Res;