[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp

[Chris Lattner]

Changes in directory llvm/lib/CodeGen/SelectionDAG:

SelectionDAGISel.cpp updated: 1.406 -> 1.407
---
Log message:

Fix PR1316: http://llvm.org/PR1316 


---
Diffs of the changes:  (+4 -4)

 SelectionDAGISel.cpp |    8 ++++----
 1 files changed, 4 insertions(+), 4 deletions(-)


Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.406 llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.407
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.406	Sun Apr  8 17:23:26 2007
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp	Sun Apr  8 19:33:58 2007
@@ -2439,8 +2439,6 @@
     return 0;
   }
   case Intrinsic::bit_part_select: {
-    // MVT::ValueType Ty = getValue(I.getOperand(1)).getValueType();
-    // setValue(&I, DAG.getTargetConstant(0, Ty));
     // Currently not implemented: just abort
     assert(0 && "bit_part_select intrinsic not implemented");
     abort();
@@ -2687,7 +2685,8 @@
 /// values added into it.
 void RegsForValue::AddInlineAsmOperands(unsigned Code, SelectionDAG &DAG,
                                         std::vector<SDOperand> &Ops) const {
-  Ops.push_back(DAG.getTargetConstant(Code | (Regs.size() << 3), MVT::i32));
+  MVT::ValueType IntPtrTy = DAG.getTargetLoweringInfo().getPointerTy();
+  Ops.push_back(DAG.getTargetConstant(Code | (Regs.size() << 3), IntPtrTy));
   for (unsigned i = 0, e = Regs.size(); i != e; ++i)
     Ops.push_back(DAG.getRegister(Regs[i], RegVT));
 }
@@ -4524,8 +4523,9 @@
       }
       
       // Add this to the output node.
+      MVT::ValueType IntPtrTy = DAG.getTargetLoweringInfo().getPointerTy();
       Ops.push_back(DAG.getTargetConstant(4/*MEM*/ | (SelOps.size() << 3),
-                                          MVT::i32));
+                                          IntPtrTy));
       Ops.insert(Ops.end(), SelOps.begin(), SelOps.end());
       i += 2;
     }