[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCCallingConv.td PPCISelLowering.cpp PPCInstr64Bit.td PPCInstrInfo.td PPCRegisterInfo.cpp
Nicolas Geoffray
nicolas.geoffray at lip6.fr
Tue Apr 3 03:27:24 PDT 2007
Changes in directory llvm/lib/Target/PowerPC:
PPCCallingConv.td updated: 1.1 -> 1.2
PPCISelLowering.cpp updated: 1.265 -> 1.266
PPCInstr64Bit.td updated: 1.42 -> 1.43
PPCInstrInfo.td updated: 1.276 -> 1.277
PPCRegisterInfo.cpp updated: 1.118 -> 1.119
---
Log message:
The ELF ABI specifies F1-F8 registers as argument registers for double, not
F1-F10. This affects only ELF, not MachO.
---
Diffs of the changes: (+12 -10)
PPCCallingConv.td | 4 ++--
PPCISelLowering.cpp | 6 +++---
PPCInstr64Bit.td | 2 +-
PPCInstrInfo.td | 2 +-
PPCRegisterInfo.cpp | 8 +++++---
5 files changed, 12 insertions(+), 10 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCCallingConv.td
diff -u llvm/lib/Target/PowerPC/PPCCallingConv.td:1.1 llvm/lib/Target/PowerPC/PPCCallingConv.td:1.2
--- llvm/lib/Target/PowerPC/PPCCallingConv.td:1.1 Mon Mar 5 18:59:59 2007
+++ llvm/lib/Target/PowerPC/PPCCallingConv.td Tue Apr 3 05:27:07 2007
@@ -44,8 +44,8 @@
// Darwin passes FP values in F1 - F13
CCIfType<[f32, f64], CCIfSubtarget<"isMachoABI()",
CCAssignToReg<[F1, F2, F3, F4, F5, F6, F7, F8,F9,F10,F11,F12,F13]>>>,
- // Other sub-targets pass FP values in F1-10.
- CCIfType<[f32, f64], CCAssignToReg<[F1, F2, F3, F4, F5, F6, F7, F8, F9,F10]>>,
+ // Other sub-targets pass FP values in F1-F8.
+ CCIfType<[f32, f64], CCAssignToReg<[F1, F2, F3, F4, F5, F6, F7, F8]>>,
// The first 12 Vector arguments are passed in altivec registers.
CCIfType<[v16i8, v8i16, v4i32, v4f32],
Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.265 llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.266
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.265 Fri Mar 30 18:15:24 2007
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp Tue Apr 3 05:27:07 2007
@@ -1113,7 +1113,7 @@
static const unsigned FPR[] = {
PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
- PPC::F8, PPC::F9, PPC::F10
+ PPC::F8
};
return FPR;
}
@@ -1154,7 +1154,7 @@
};
const unsigned Num_GPR_Regs = sizeof(GPR_32)/sizeof(GPR_32[0]);
- const unsigned Num_FPR_Regs = isMachoABI ? 13 : 10;
+ const unsigned Num_FPR_Regs = isMachoABI ? 13 : 8;
const unsigned Num_VR_Regs = sizeof( VR)/sizeof( VR[0]);
unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
@@ -1410,7 +1410,7 @@
PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
};
const unsigned NumGPRs = sizeof(GPR_32)/sizeof(GPR_32[0]);
- const unsigned NumFPRs = isMachoABI ? 13 : 10;
+ const unsigned NumFPRs = isMachoABI ? 13 : 8;
const unsigned NumVRs = sizeof( VR)/sizeof( VR[0]);
const unsigned *GPR = isPPC64 ? GPR_64 : GPR_32;
Index: llvm/lib/Target/PowerPC/PPCInstr64Bit.td
diff -u llvm/lib/Target/PowerPC/PPCInstr64Bit.td:1.42 llvm/lib/Target/PowerPC/PPCInstr64Bit.td:1.43
--- llvm/lib/Target/PowerPC/PPCInstr64Bit.td:1.42 Sat Mar 24 23:44:03 2007
+++ llvm/lib/Target/PowerPC/PPCInstr64Bit.td Tue Apr 3 05:27:07 2007
@@ -91,7 +91,7 @@
let isCall = 1, noResults = 1, PPC970_Unit = 7,
// All calls clobber the PPC64 non-callee saved registers.
Defs = [X0,X2,X3,X4,X5,X6,X7,X8,X9,X10,X11,X12,
- F0,F1,F2,F3,F4,F5,F6,F7,F8,F9,F10,
+ F0,F1,F2,F3,F4,F5,F6,F7,F8,
V0,V1,V2,V3,V4,V5,V6,V7,V8,V9,V10,V11,V12,V13,V14,V15,V16,V17,V18,V19,
LR8,CTR8,
CR0,CR1,CR5,CR6,CR7] in {
Index: llvm/lib/Target/PowerPC/PPCInstrInfo.td
diff -u llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.276 llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.277
--- llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.276 Tue Feb 27 07:01:19 2007
+++ llvm/lib/Target/PowerPC/PPCInstrInfo.td Tue Apr 3 05:27:07 2007
@@ -396,7 +396,7 @@
let isCall = 1, noResults = 1, PPC970_Unit = 7,
// All calls clobber the non-callee saved registers...
Defs = [R0,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,
- F0,F1,F2,F3,F4,F5,F6,F7,F8,F9,F10,
+ F0,F1,F2,F3,F4,F5,F6,F7,F8,
V0,V1,V2,V3,V4,V5,V6,V7,V8,V9,V10,V11,V12,V13,V14,V15,V16,V17,V18,V19,
LR,CTR,
CR0,CR1,CR5,CR6,CR7] in {
Index: llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
diff -u llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.118 llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.119
--- llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp:1.118 Wed Mar 21 11:44:14 2007
+++ llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp Tue Apr 3 05:27:07 2007
@@ -278,7 +278,8 @@
PPC::R24, PPC::R25, PPC::R26, PPC::R27,
PPC::R28, PPC::R29, PPC::R30, PPC::R31,
- PPC::F11, PPC::F12, PPC::F13,
+ PPC::F9,
+ PPC::F10, PPC::F11, PPC::F12, PPC::F13,
PPC::F14, PPC::F15, PPC::F16, PPC::F17,
PPC::F18, PPC::F19, PPC::F20, PPC::F21,
PPC::F22, PPC::F23, PPC::F24, PPC::F25,
@@ -320,8 +321,9 @@
PPC::X20, PPC::X21, PPC::X22, PPC::X23,
PPC::X24, PPC::X25, PPC::X26, PPC::X27,
PPC::X28, PPC::X29, PPC::X30, PPC::X31,
-
- PPC::F11, PPC::F12, PPC::F13,
+
+ PPC::F9,
+ PPC::F10, PPC::F11, PPC::F12, PPC::F13,
PPC::F14, PPC::F15, PPC::F16, PPC::F17,
PPC::F18, PPC::F19, PPC::F20, PPC::F21,
PPC::F22, PPC::F23, PPC::F24, PPC::F25,
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