[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelLowering.cpp PPCISelLowering.h

[Chris Lattner]

Changes in directory llvm/lib/Target/PowerPC:

PPCISelLowering.cpp updated: 1.264 -> 1.265
PPCISelLowering.h updated: 1.63 -> 1.64
---
Log message:

implement the new addressing mode description hook.


---
Diffs of the changes:  (+38 -1)

 PPCISelLowering.cpp |   35 ++++++++++++++++++++++++++++++++++-
 PPCISelLowering.h   |    4 ++++
 2 files changed, 38 insertions(+), 1 deletion(-)


Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.264 llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.265
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.264	Tue Mar 27 11:33:08 2007
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp	Fri Mar 30 18:15:24 2007
@@ -3199,6 +3199,39 @@
   return TargetLowering::isOperandValidForConstraint(Op, Letter, DAG);
 }
 
+// isLegalAddressingMode - Return true if the addressing mode represented
+// by AM is legal for this target, for a load/store of the specified type.
+bool PPCTargetLowering::isLegalAddressingMode(const AddrMode &AM, 
+                                              const Type *Ty) const {
+  // FIXME: PPC does not allow r+i addressing modes for vectors!
+  
+  // PPC allows a sign-extended 16-bit immediate field.
+  if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
+    return false;
+  
+  // No global is ever allowed as a base.
+  if (AM.BaseGV)
+    return false;
+  
+  // PPC only support r+r, 
+  switch (AM.Scale) {
+  case 0:  // "r+i" or just "i", depending on HasBaseReg.
+    break;
+  case 1:
+    if (AM.HasBaseReg && AM.BaseOffs)  // "r+r+i" is not allowed.
+      return false;
+    // Otherwise we have r+r or r+i.
+    break;
+  case 2:
+    if (AM.HasBaseReg || AM.BaseOffs)  // 2*r+r  or  2*r+i is not allowed.
+      return false;
+    // Allow 2*r as r+r.
+    break;
+  }
+  
+  return true;
+}
+
 /// isLegalAddressImmediate - Return true if the integer value can be used
 /// as the offset of the target addressing mode for load / store of the
 /// given type.
@@ -3208,7 +3241,7 @@
 }
 
 bool PPCTargetLowering::isLegalAddressImmediate(llvm::GlobalValue* GV) const {
-  return TargetLowering::isLegalAddressImmediate(GV); 
+  return false; 
 }
 
 SDOperand PPCTargetLowering::LowerFRAMEADDR(SDOperand Op, SelectionDAG &DAG)


Index: llvm/lib/Target/PowerPC/PPCISelLowering.h
diff -u llvm/lib/Target/PowerPC/PPCISelLowering.h:1.63 llvm/lib/Target/PowerPC/PPCISelLowering.h:1.64
--- llvm/lib/Target/PowerPC/PPCISelLowering.h:1.63	Sat Mar 24 21:14:49 2007
+++ llvm/lib/Target/PowerPC/PPCISelLowering.h	Fri Mar 30 18:15:24 2007
@@ -236,6 +236,10 @@
     SDOperand isOperandValidForConstraint(SDOperand Op, char ConstraintLetter,
                                           SelectionDAG &DAG);
 
+    /// isLegalAddressingMode - Return true if the addressing mode represented
+    /// by AM is legal for this target, for a load/store of the specified type.
+    virtual bool isLegalAddressingMode(const AddrMode &AM, const Type *Ty)const;
+    
     /// isLegalAddressImmediate - Return true if the integer value can be used
     /// as the offset of the target addressing mode for load / store of the
     /// given type.