[llvm-commits] CVS: llvm/lib/Transforms/Scalar/InstructionCombining.cpp

[Chris Lattner]

On Mar 22, 2007, at 1:57 PM, Reid Spencer wrote:
> @@ -7008,10 +7008,8 @@
>        case Instruction::ZExt: {
>          // We need to emit an AND to clear the high bits.
>          assert(SrcBitSize < DestBitSize && "Not a zext?");
> -        Constant *C =
> -          ConstantInt::get(Type::Int64Ty, (1ULL << SrcBitSize)-1);
> -        if (DestBitSize < 64)
> -          C = ConstantExpr::getTrunc(C, DestTy);
> +        Constant *C = ConstantInt::get(APInt::getAllOnesValue 
> (SrcBitSize));
> +        C = ConstantExpr::getZExt(C, DestTy);

This should be done with APInt's, not with ConstantExpr.

>          return BinaryOperator::createAnd(Res, C);
>        }
>        case Instruction::SExt:
> @@ -7190,7 +7190,8 @@
>          unsigned ShAmt = ShAmtV->getZExtValue();
>
>          // Get a mask for the bits shifting in.
> -        uint64_t Mask = (~0ULL >> (64-ShAmt)) << DestBitWidth;
> +        APInt Mask(APInt::getAllOnesValue(SrcBitWidth).lshr(
> +                     SrcBitWidth-ShAmt).shl(DestBitWidth));

Please use the new methods.

>          Value* SrcIOp0 = SrcI->getOperand(0);
>          if (SrcI->hasOneUse() && MaskedValueIsZero(SrcIOp0, Mask)) {
>            if (ShAmt >= DestBitWidth)        // All zeros.
> @@ -7249,8 +7250,8 @@
>        // If we're actually extending zero bits and the trunc is a  
> no-op
>        if (MidSize < DstSize && SrcSize == DstSize) {
>          // Replace both of the casts with an And of the type mask.
> -        uint64_t AndValue = cast<IntegerType>(CSrc->getType())- 
> >getBitMask();
> -        Constant *AndConst = ConstantInt::get(A->getType(),  
> AndValue);
> +        APInt AndValue(APInt::getAllOnesValue(MidSize).zext 
> (SrcSize));
> +        Constant *AndConst = ConstantInt::get(AndValue);

Likewise

-Chris