[llvm-commits] CVS: llvm/lib/Target/X86/X86InstrFPStack.td X86InstrInfo.td X86InstrSSE.td

[Evan Cheng]

Changes in directory llvm/lib/Target/X86:

X86InstrFPStack.td updated: 1.8 -> 1.9
X86InstrInfo.td updated: 1.299 -> 1.300
X86InstrSSE.td updated: 1.178 -> 1.179
---
Log message:

Mark re-materializable instructions.

---
Diffs of the changes:  (+6 -0)

 X86InstrFPStack.td |    2 ++
 X86InstrInfo.td    |    2 ++
 X86InstrSSE.td     |    2 ++
 3 files changed, 6 insertions(+)


Index: llvm/lib/Target/X86/X86InstrFPStack.td
diff -u llvm/lib/Target/X86/X86InstrFPStack.td:1.8 llvm/lib/Target/X86/X86InstrFPStack.td:1.9
--- llvm/lib/Target/X86/X86InstrFPStack.td:1.8	Fri Oct 13 16:14:26 2006
+++ llvm/lib/Target/X86/X86InstrFPStack.td	Tue Mar 20 19:16:56 2007
@@ -413,10 +413,12 @@
 def FXCH    : FPI<0xC8, AddRegFrm, (ops RST:$op), "fxch $op">, D9;
 
 // Floating point constant loads.
+let isReMaterializable = 1 in {
 def FpLD0 : FpI<(ops RFP:$dst), ZeroArgFP,
                 [(set RFP:$dst, fp64imm0)]>;
 def FpLD1 : FpI<(ops RFP:$dst), ZeroArgFP,
                 [(set RFP:$dst, fp64imm1)]>;
+}
 
 def FLD0 : FPI<0xEE, RawFrm, (ops), "fldz">, D9;
 def FLD1 : FPI<0xE8, RawFrm, (ops), "fld1">, D9;


Index: llvm/lib/Target/X86/X86InstrInfo.td
diff -u llvm/lib/Target/X86/X86InstrInfo.td:1.299 llvm/lib/Target/X86/X86InstrInfo.td:1.300
--- llvm/lib/Target/X86/X86InstrInfo.td:1.299	Fri Jan 26 08:34:52 2007
+++ llvm/lib/Target/X86/X86InstrInfo.td	Tue Mar 20 19:16:56 2007
@@ -601,6 +601,7 @@
                 "mov{w} {$src, $dst|$dst, $src}", []>, OpSize;
 def MOV32rr : I<0x89, MRMDestReg, (ops GR32:$dst, GR32:$src),
                 "mov{l} {$src, $dst|$dst, $src}", []>;
+let isReMaterializable = 1 in {
 def MOV8ri  : Ii8 <0xB0, AddRegFrm, (ops GR8 :$dst, i8imm :$src),
                    "mov{b} {$src, $dst|$dst, $src}",
                    [(set GR8:$dst, imm:$src)]>;
@@ -610,6 +611,7 @@
 def MOV32ri : Ii32<0xB8, AddRegFrm, (ops GR32:$dst, i32imm:$src),
                    "mov{l} {$src, $dst|$dst, $src}",
                    [(set GR32:$dst, imm:$src)]>;
+}
 def MOV8mi  : Ii8 <0xC6, MRM0m, (ops i8mem :$dst, i8imm :$src),
                    "mov{b} {$src, $dst|$dst, $src}",
                    [(store (i8 imm:$src), addr:$dst)]>;


Index: llvm/lib/Target/X86/X86InstrSSE.td
diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.178 llvm/lib/Target/X86/X86InstrSSE.td:1.179
--- llvm/lib/Target/X86/X86InstrSSE.td:1.178	Sun Mar  4 00:13:52 2007
+++ llvm/lib/Target/X86/X86InstrSSE.td	Tue Mar 20 19:16:56 2007
@@ -1666,6 +1666,7 @@
 
 // Alias instructions that map zero vector to pxor / xorp* for sse.
 // FIXME: remove when we can teach regalloc that xor reg, reg is ok.
+let isReMaterializable = 1 in {
 def V_SET0 : PSI<0x57, MRMInitReg, (ops VR128:$dst),
                  "xorps $dst, $dst",
                  [(set VR128:$dst, (v4f32 immAllZerosV))]>;
@@ -1673,6 +1674,7 @@
 def V_SETALLONES : PDI<0x76, MRMInitReg, (ops VR128:$dst),
                        "pcmpeqd $dst, $dst",
                        [(set VR128:$dst, (v2f64 immAllOnesV))]>;
+}
 
 // FR32 / FR64 to 128-bit vector conversion.
 def MOVSS2PSrr : SSI<0x10, MRMSrcReg, (ops VR128:$dst, FR32:$src),