[llvm-commits] CVS: llvm/lib/Target/ARM/ARMISelLowering.cpp ARMInstrInfo.td ARMInstrThumb.td

[Lauro Ramos Venancio]

Changes in directory llvm/lib/Target/ARM:

ARMISelLowering.cpp updated: 1.26 -> 1.27
ARMInstrInfo.td updated: 1.92 -> 1.93
ARMInstrThumb.td updated: 1.17 -> 1.18
---
Log message:

bugfix: When the source register of CALL_NOLINK was LR, the following code was emitted:
    mov lr, pc
    bx lr
So, the function was not called.



---
Diffs of the changes:  (+28 -19)

 ARMISelLowering.cpp |   29 ++++++++++++++++++-----------
 ARMInstrInfo.td     |   10 +++++-----
 ARMInstrThumb.td    |    8 +++++---
 3 files changed, 28 insertions(+), 19 deletions(-)


Index: llvm/lib/Target/ARM/ARMISelLowering.cpp
diff -u llvm/lib/Target/ARM/ARMISelLowering.cpp:1.26 llvm/lib/Target/ARM/ARMISelLowering.cpp:1.27
--- llvm/lib/Target/ARM/ARMISelLowering.cpp:1.26	Mon Mar 19 21:25:53 2007
+++ llvm/lib/Target/ARM/ARMISelLowering.cpp	Tue Mar 20 12:57:23 2007
@@ -544,6 +544,24 @@
       Callee = DAG.getTargetExternalSymbol(Sym, getPointerTy());
   }
 
+  // FIXME: handle tail calls differently.
+  unsigned CallOpc;
+  if (Subtarget->isThumb()) {
+    if (!Subtarget->hasV5TOps() && (!isDirect || isARMFunc))
+      CallOpc = ARMISD::CALL_NOLINK;
+    else
+      CallOpc = isARMFunc ? ARMISD::CALL : ARMISD::tCALL;
+  } else {
+    CallOpc = (isDirect || Subtarget->hasV5TOps())
+      ? ARMISD::CALL : ARMISD::CALL_NOLINK;
+  }
+  if (CallOpc == ARMISD::CALL_NOLINK) {
+    // On CALL_NOLINK we must move PC to LR
+    Chain = DAG.getCopyToReg(Chain, ARM::LR,
+                             DAG.getRegister(ARM::PC, MVT::i32), InFlag);
+    InFlag = Chain.getValue(1);
+  }
+
   std::vector<MVT::ValueType> NodeTys;
   NodeTys.push_back(MVT::Other);   // Returns a chain
   NodeTys.push_back(MVT::Flag);    // Returns a flag for retval copy to use.
@@ -558,17 +576,6 @@
     Ops.push_back(DAG.getRegister(RegsToPass[i].first,
                                   RegsToPass[i].second.getValueType()));
 
-  // FIXME: handle tail calls differently.
-  unsigned CallOpc;
-  if (Subtarget->isThumb()) {
-    if (!Subtarget->hasV5TOps() && (!isDirect || isARMFunc))
-      CallOpc = ARMISD::CALL_NOLINK;
-    else
-      CallOpc = isARMFunc ? ARMISD::CALL : ARMISD::tCALL;
-  } else {
-    CallOpc = (isDirect || Subtarget->hasV5TOps())
-      ? ARMISD::CALL : ARMISD::CALL_NOLINK;
-  }
   if (InFlag.Val)
     Ops.push_back(InFlag);
   Chain = DAG.getNode(CallOpc, NodeTys, &Ops[0], Ops.size());


Index: llvm/lib/Target/ARM/ARMInstrInfo.td
diff -u llvm/lib/Target/ARM/ARMInstrInfo.td:1.92 llvm/lib/Target/ARM/ARMInstrInfo.td:1.93
--- llvm/lib/Target/ARM/ARMInstrInfo.td:1.92	Tue Mar 20 03:11:30 2007
+++ llvm/lib/Target/ARM/ARMInstrInfo.td	Tue Mar 20 12:57:23 2007
@@ -370,8 +370,6 @@
   : I<ops, AddrMode3, Size4Bytes, IndexModeNone, asm, "", pattern>;
 class AI4<dag ops, string asm, list<dag> pattern>
   : I<ops, AddrMode4, Size4Bytes, IndexModeNone, asm, "", pattern>;
-class AIx2<dag ops, string asm, list<dag> pattern>
-  : I<ops, AddrModeNone, Size8Bytes, IndexModeNone, asm, "", pattern>;
 class AI1x2<dag ops, string asm, list<dag> pattern>
   : I<ops, AddrMode1, Size8Bytes, IndexModeNone, asm, "", pattern>;
 
@@ -546,10 +544,12 @@
   def BLX : AI<(ops GPR:$dst, variable_ops),
                "blx $dst",
                [(ARMcall GPR:$dst)]>, Requires<[IsARM, HasV5T]>;
-  // ARMv4T
-  def BX : AIx2<(ops GPR:$dst, variable_ops),
-                "mov lr, pc\n\tbx $dst",
+  let Uses = [LR] in {
+    // ARMv4T
+    def BX : AI<(ops GPR:$dst, variable_ops),
+                "bx $dst",
                 [(ARMcall_nolink GPR:$dst)]>;
+  }
 }
 
 let isBranch = 1, isTerminator = 1, isBarrier = 1 in {


Index: llvm/lib/Target/ARM/ARMInstrThumb.td
diff -u llvm/lib/Target/ARM/ARMInstrThumb.td:1.17 llvm/lib/Target/ARM/ARMInstrThumb.td:1.18
--- llvm/lib/Target/ARM/ARMInstrThumb.td:1.17	Mon Mar 19 02:48:02 2007
+++ llvm/lib/Target/ARM/ARMInstrThumb.td	Tue Mar 20 12:57:23 2007
@@ -189,10 +189,12 @@
   def tBLXr : TI<(ops GPR:$dst, variable_ops),
                   "blx $dst",
                   [(ARMtcall GPR:$dst)]>, Requires<[HasV5T]>;
-  // ARMv4T
-  def tBX : TIx2<(ops GPR:$dst, variable_ops),
-                  "cpy lr, pc\n\tbx $dst",
+  let Uses = [LR] in {
+    // ARMv4T
+    def tBX : TI<(ops GPR:$dst, variable_ops),
+                  "bx $dst",
                   [(ARMcall_nolink GPR:$dst)]>;
+  }
 }
 
 let isBranch = 1, isTerminator = 1, isBarrier = 1 in {