[llvm-commits] CVS: llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp ARMInstrInfo.td ARMInstrThumb.td

[Evan Cheng]

Changes in directory llvm/lib/Target/ARM:

ARMISelDAGToDAG.cpp updated: 1.108 -> 1.109
ARMInstrInfo.td updated: 1.89 -> 1.90
ARMInstrThumb.td updated: 1.15 -> 1.16
---
Log message:

Special LDR instructions to load from non-pc-relative constantpools. These are
rematerializable. Only used for constant generation for now.

---
Diffs of the changes:  (+12 -2)

 ARMISelDAGToDAG.cpp |    4 ++--
 ARMInstrInfo.td     |    5 +++++
 ARMInstrThumb.td    |    5 +++++
 3 files changed, 12 insertions(+), 2 deletions(-)


Index: llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
diff -u llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp:1.108 llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp:1.109
--- llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp:1.108	Tue Mar 13 16:05:54 2007
+++ llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp	Mon Mar 19 02:20:03 2007
@@ -551,7 +551,7 @@
 
       SDNode *ResNode;
       if (Subtarget->isThumb())
-        ResNode = CurDAG->getTargetNode(ARM::tLDRpci, MVT::i32, MVT::Other,
+        ResNode = CurDAG->getTargetNode(ARM::tLDRcp, MVT::i32, MVT::Other,
                                         CPIdx, CurDAG->getEntryNode());
       else {
         SDOperand Ops[] = {
@@ -560,7 +560,7 @@
           CurDAG->getTargetConstant(0, MVT::i32),
           CurDAG->getEntryNode()
         };
-        ResNode = CurDAG->getTargetNode(ARM::LDR, MVT::i32, MVT::Other, Ops, 4);
+        ResNode=CurDAG->getTargetNode(ARM::LDRcp, MVT::i32, MVT::Other, Ops, 4);
       }
       ReplaceUses(Op, SDOperand(ResNode, 0));
       return NULL;


Index: llvm/lib/Target/ARM/ARMInstrInfo.td
diff -u llvm/lib/Target/ARM/ARMInstrInfo.td:1.89 llvm/lib/Target/ARM/ARMInstrInfo.td:1.90
--- llvm/lib/Target/ARM/ARMInstrInfo.td:1.89	Mon Mar 19 02:09:02 2007
+++ llvm/lib/Target/ARM/ARMInstrInfo.td	Mon Mar 19 02:20:03 2007
@@ -580,6 +580,11 @@
                "ldr $dst, $addr",
                [(set GPR:$dst, (load addrmode2:$addr))]>;
 
+// Special LDR for loads from non-pc-relative constpools.
+let isReMaterializable = 1 in
+def LDRcp : AI2<(ops GPR:$dst, addrmode2:$addr),
+                 "ldr $dst, $addr", []>;
+
 // Loads with zero extension
 def LDRH  : AI3<(ops GPR:$dst, addrmode3:$addr),
                  "ldrh $dst, $addr",


Index: llvm/lib/Target/ARM/ARMInstrThumb.td
diff -u llvm/lib/Target/ARM/ARMInstrThumb.td:1.15 llvm/lib/Target/ARM/ARMInstrThumb.td:1.16
--- llvm/lib/Target/ARM/ARMInstrThumb.td:1.15	Mon Mar 19 02:09:02 2007
+++ llvm/lib/Target/ARM/ARMInstrThumb.td	Mon Mar 19 02:20:03 2007
@@ -248,6 +248,11 @@
 def tLDRpci : TIs<(ops GPR:$dst, i32imm:$addr),
                   "ldr $dst, $addr",
                   [(set GPR:$dst, (load (ARMWrapper tconstpool:$addr)))]>;
+
+// Special LDR for loads from non-pc-relative constpools.
+let isReMaterializable = 1 in
+def tLDRcp  : TIs<(ops GPR:$dst, i32imm:$addr),
+                  "ldr $dst, $addr", []>;
 } // isLoad
 
 let isStore = 1 in {