[llvm-commits] CVS: llvm/lib/Target/Alpha/AlphaISelLowering.cpp

[Anton Korobeynikov]

Changes in directory llvm/lib/Target/Alpha:

AlphaISelLowering.cpp updated: 1.83 -> 1.84
---
Log message:

Refactoring of formal parameter flags. Enable properly use of 
zext/sext/aext stuff.


---
Diffs of the changes:  (+4 -2)

 AlphaISelLowering.cpp |    6 ++++--
 1 files changed, 4 insertions(+), 2 deletions(-)


Index: llvm/lib/Target/Alpha/AlphaISelLowering.cpp
diff -u llvm/lib/Target/Alpha/AlphaISelLowering.cpp:1.83 llvm/lib/Target/Alpha/AlphaISelLowering.cpp:1.84
--- llvm/lib/Target/Alpha/AlphaISelLowering.cpp:1.83	Thu Feb 22 08:56:36 2007
+++ llvm/lib/Target/Alpha/AlphaISelLowering.cpp	Wed Mar  7 10:25:08 2007
@@ -337,10 +337,12 @@
     case MVT::i32:
       // Promote the integer to 64 bits.  If the input type is signed use a
       // sign extend, otherwise use a zero extend.
-      if (Args[i].isSigned)
+      if (Args[i].isSExt)
         Args[i].Node = DAG.getNode(ISD::SIGN_EXTEND, MVT::i64, Args[i].Node);
-      else
+      else if (Args[i].isZExt)
         Args[i].Node = DAG.getNode(ISD::ZERO_EXTEND, MVT::i64, Args[i].Node);
+      else
+        Args[i].Node = DAG.getNode(ISD::ANY_EXTEND, MVT::i64, Args[i].Node);
       break;
     case MVT::i64:
     case MVT::f64: