[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp

[Chris Lattner]

Changes in directory llvm/lib/Target/X86:

X86ISelLowering.cpp updated: 1.357 -> 1.358
---
Log message:

argument lowering should copy from the vreg shadows of live-in arguments
passed in registers, not directly from the pregs themselves.


---
Diffs of the changes:  (+7 -7)

 X86ISelLowering.cpp |   14 +++++++-------
 1 files changed, 7 insertions(+), 7 deletions(-)


Index: llvm/lib/Target/X86/X86ISelLowering.cpp
diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.357 llvm/lib/Target/X86/X86ISelLowering.cpp:1.358
--- llvm/lib/Target/X86/X86ISelLowering.cpp:1.357	Thu Mar  1 10:29:22 2007
+++ llvm/lib/Target/X86/X86ISelLowering.cpp	Thu Mar  1 23:12:29 2007
@@ -627,8 +627,8 @@
         RC = X86::VR128RegisterClass;
       }
       
-      SDOperand ArgValue = DAG.getCopyFromReg(Root, VA.getLocReg(), RegVT);
-      AddLiveIn(DAG.getMachineFunction(), VA.getLocReg(), RC);
+      unsigned Reg = AddLiveIn(DAG.getMachineFunction(), VA.getLocReg(), RC);
+      SDOperand ArgValue = DAG.getCopyFromReg(Root, Reg, RegVT);
       
       // If this is an 8 or 16-bit value, it is really passed promoted to 32
       // bits.  Insert an assert[sz]ext to capture this, then truncate to the
@@ -877,8 +877,8 @@
         RC = X86::VR128RegisterClass;
       }
       
-      SDOperand ArgValue = DAG.getCopyFromReg(Root, VA.getLocReg(), RegVT);
-      AddLiveIn(DAG.getMachineFunction(), VA.getLocReg(), RC);
+      unsigned Reg = AddLiveIn(DAG.getMachineFunction(), VA.getLocReg(), RC);
+      SDOperand ArgValue = DAG.getCopyFromReg(Root, Reg, RegVT);
       
       // If this is an 8 or 16-bit value, it is really passed promoted to 32
       // bits.  Insert an assert[sz]ext to capture this, then truncate to the
@@ -1116,9 +1116,9 @@
         assert(MVT::isVector(RegVT));
         RC = X86::VR128RegisterClass;
       }
-      
-      SDOperand ArgValue = DAG.getCopyFromReg(Root, VA.getLocReg(), RegVT);
-      AddLiveIn(DAG.getMachineFunction(), VA.getLocReg(), RC);
+
+      unsigned Reg = AddLiveIn(DAG.getMachineFunction(), VA.getLocReg(), RC);
+      SDOperand ArgValue = DAG.getCopyFromReg(Root, Reg, RegVT);
       
       // If this is an 8 or 16-bit value, it is really passed promoted to 32
       // bits.  Insert an assert[sz]ext to capture this, then truncate to the