[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp

[Chris Lattner]

Changes in directory llvm/lib/Target/X86:

X86ISelLowering.cpp updated: 1.354 -> 1.355
---
Log message:

use high-level functions in CCState


---
Diffs of the changes:  (+6 -15)

 X86ISelLowering.cpp |   21 ++++++---------------
 1 files changed, 6 insertions(+), 15 deletions(-)


Index: llvm/lib/Target/X86/X86ISelLowering.cpp
diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.354 llvm/lib/Target/X86/X86ISelLowering.cpp:1.355
--- llvm/lib/Target/X86/X86ISelLowering.cpp:1.354	Wed Feb 28 01:00:42 2007
+++ llvm/lib/Target/X86/X86ISelLowering.cpp	Wed Feb 28 01:09:55 2007
@@ -438,15 +438,8 @@
   SmallVector<CCValAssign, 16> RVLocs;
   unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv();
   CCState CCInfo(CC, getTargetMachine(), RVLocs);
+  CCInfo.AnalyzeReturn(Op.Val, RetCC_X86);
   
-  // Determine which register each value should be copied into.
-  for (unsigned i = 0; i != Op.getNumOperands() / 2; ++i) {
-    MVT::ValueType VT = Op.getOperand(i*2+1).getValueType();
-    if (RetCC_X86(i, VT, VT, CCValAssign::Full,
-                  cast<ConstantSDNode>(Op.getOperand(i*2+2))->getValue(),
-                  CCInfo))
-      assert(0 && "Unhandled result type!");
-  }
   
   // If this is the first return lowered for this function, add the regs to the
   // liveout set for the function.
@@ -521,16 +514,14 @@
 SDNode *X86TargetLowering::
 LowerCallResult(SDOperand Chain, SDOperand InFlag, SDNode *TheCall, 
                 unsigned CallingConv, SelectionDAG &DAG) {
-  SmallVector<SDOperand, 8> ResultVals;
-
+  
+  // Assign locations to each value returned by this call.
   SmallVector<CCValAssign, 16> RVLocs;
   CCState CCInfo(CallingConv, getTargetMachine(), RVLocs);
+  CCInfo.AnalyzeCallResult(TheCall, RetCC_X86);
+
   
-  for (unsigned i = 0, e = TheCall->getNumValues() - 1; i != e; ++i) {
-    MVT::ValueType VT = TheCall->getValueType(i);
-    if (RetCC_X86(i, VT, VT, CCValAssign::Full, 0, CCInfo))
-      assert(0 && "Unhandled result type!");
-  }
+  SmallVector<SDOperand, 8> ResultVals;
   
   // Copy all of the result registers out of their specified physreg.
   if (RVLocs.size() != 1 || RVLocs[0].getLocReg() != X86::ST0) {