[llvm-commits] CVS: llvm/lib/CodeGen/PrologEpilogInserter.cpp RegisterScavenging.cpp

[Evan Cheng]

Changes in directory llvm/lib/CodeGen:

PrologEpilogInserter.cpp updated: 1.69 -> 1.70
RegisterScavenging.cpp updated: 1.3 -> 1.4
---
Log message:

forward() should not increment internal iterator. Its client may insert instruction between now and next forward() call.

---
Diffs of the changes:  (+26 -5)

 PrologEpilogInserter.cpp |    2 +-
 RegisterScavenging.cpp   |   29 +++++++++++++++++++++++++----
 2 files changed, 26 insertions(+), 5 deletions(-)


Index: llvm/lib/CodeGen/PrologEpilogInserter.cpp
diff -u llvm/lib/CodeGen/PrologEpilogInserter.cpp:1.69 llvm/lib/CodeGen/PrologEpilogInserter.cpp:1.70
--- llvm/lib/CodeGen/PrologEpilogInserter.cpp:1.69	Thu Feb 22 19:11:26 2007
+++ llvm/lib/CodeGen/PrologEpilogInserter.cpp	Mon Feb 26 19:58:04 2007
@@ -455,7 +455,7 @@
         }
       // Update register states.
       if (MRI.requiresRegisterScavenging())
-        RS.forward();
+        RS.forward(I);
     }
   }
 }


Index: llvm/lib/CodeGen/RegisterScavenging.cpp
diff -u llvm/lib/CodeGen/RegisterScavenging.cpp:1.3 llvm/lib/CodeGen/RegisterScavenging.cpp:1.4
--- llvm/lib/CodeGen/RegisterScavenging.cpp:1.3	Sun Feb 25 03:47:31 2007
+++ llvm/lib/CodeGen/RegisterScavenging.cpp	Mon Feb 26 19:58:04 2007
@@ -22,10 +22,11 @@
 #include "llvm/Target/MRegisterInfo.h"
 #include "llvm/Target/TargetInstrInfo.h"
 #include "llvm/Target/TargetMachine.h"
+#include "llvm/ADT/STLExtras.h"
 using namespace llvm;
 
 RegScavenger::RegScavenger(MachineBasicBlock *mbb)
-  : MBB(mbb), MBBI(mbb->begin()) {
+  : MBB(mbb), MBBIInited(false) {
   const MachineFunction &MF = *MBB->getParent();
   const TargetMachine &TM = MF.getTarget();
   const MRegisterInfo *RegInfo = TM.getRegisterInfo();
@@ -52,6 +53,14 @@
 }
 
 void RegScavenger::forward() {
+  assert(MBBI != MBB->end() && "Already at the end of the basic block!");
+  // Move ptr forward.
+  if (!MBBIInited) {
+    MBBI = MBB->begin();
+    MBBIInited = true;
+  } else
+    MBBI = next(MBBI);
+
   MachineInstr *MI = MBBI;
   // Process uses first.
   BitVector ChangedRegs(NumPhysRegs);
@@ -86,12 +95,14 @@
     if (!MO.isDead())
       setUsed(Reg);
   }
-
-  ++MBBI;
 }
 
 void RegScavenger::backward() {
-  MachineInstr *MI = --MBBI;
+  assert(MBBI != MBB->begin() && "Already at start of basic block!");
+  // Move ptr backward.
+  MBBI = prior(MBBI);
+
+  MachineInstr *MI = MBBI;
   // Process defs first.
   const TargetInstrDescriptor *TID = MI->getInstrDescriptor();
   for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
@@ -122,6 +133,16 @@
   setUsed(ChangedRegs);
 }
 
+void RegScavenger::forward(MachineBasicBlock::iterator I) {
+  while (MBBI != I)
+    forward();
+}
+
+void RegScavenger::backward(MachineBasicBlock::iterator I) {
+  while (MBBI != I)
+    backward();
+}
+
 /// CreateRegClassMask - Set the bits that represent the registers in the
 /// TargetRegisterClass.
 static void CreateRegClassMask(const TargetRegisterClass *RC, BitVector &Mask) {