[llvm-commits] CVS: llvm/lib/Target/ARM/ARMRegisterInfo.cpp ARMRegisterInfo.h

[Evan Cheng]

Changes in directory llvm/lib/Target/ARM:

ARMRegisterInfo.cpp updated: 1.70 -> 1.71
ARMRegisterInfo.h updated: 1.11 -> 1.12
---
Log message:

Add option to turn on register scavenger; By default, spills kills the register being stored.

---
Diffs of the changes:  (+20 -6)

 ARMRegisterInfo.cpp |   24 ++++++++++++++++++------
 ARMRegisterInfo.h   |    2 ++
 2 files changed, 20 insertions(+), 6 deletions(-)


Index: llvm/lib/Target/ARM/ARMRegisterInfo.cpp
diff -u llvm/lib/Target/ARM/ARMRegisterInfo.cpp:1.70 llvm/lib/Target/ARM/ARMRegisterInfo.cpp:1.71
--- llvm/lib/Target/ARM/ARMRegisterInfo.cpp:1.70	Wed Feb 21 16:54:50 2007
+++ llvm/lib/Target/ARM/ARMRegisterInfo.cpp	Thu Feb 22 19:09:11 2007
@@ -31,9 +31,13 @@
 #include "llvm/ADT/BitVector.h"
 #include "llvm/ADT/SmallVector.h"
 #include "llvm/ADT/STLExtras.h"
+#include "llvm/Support/CommandLine.h"
 #include <algorithm>
 using namespace llvm;
 
+static cl::opt<bool> EnableScavenging("enable-arm-reg-scavenging", cl::Hidden,
+                                 cl::desc("Enable register scavenging on ARM"));
+
 unsigned ARMRegisterInfo::getRegisterNumbering(unsigned RegEnum) {
   using namespace ARM;
   switch (RegEnum) {
@@ -91,8 +95,12 @@
     return false;
 
   MachineInstrBuilder MIB = BuildMI(MBB, MI, TII.get(ARM::tPUSH));
-  for (unsigned i = CSI.size(); i != 0; --i)
-    MIB.addReg(CSI[i-1].getReg());
+  for (unsigned i = CSI.size(); i != 0; --i) {
+    unsigned Reg = CSI[i-1].getReg();
+    // Add the callee-saved register as live-in. It's killed at the spill.
+    MBB.addLiveIn(Reg);
+    MIB.addReg(Reg, false/*isDef*/,false/*isImp*/,true/*isKill*/);
+  }
   return true;
 }
 
@@ -130,17 +138,17 @@
     MachineFunction &MF = *MBB.getParent();
     ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
     if (AFI->isThumbFunction())
-      BuildMI(MBB, I, TII.get(ARM::tSpill)).addReg(SrcReg)
+      BuildMI(MBB, I, TII.get(ARM::tSpill)).addReg(SrcReg, false, false, true)
         .addFrameIndex(FI).addImm(0);
     else
-      BuildMI(MBB, I, TII.get(ARM::STR)).addReg(SrcReg)
+      BuildMI(MBB, I, TII.get(ARM::STR)).addReg(SrcReg, false, false, true)
           .addFrameIndex(FI).addReg(0).addImm(0);
   } else if (RC == ARM::DPRRegisterClass) {
-    BuildMI(MBB, I, TII.get(ARM::FSTD)).addReg(SrcReg)
+    BuildMI(MBB, I, TII.get(ARM::FSTD)).addReg(SrcReg, false, false, true)
     .addFrameIndex(FI).addImm(0);
   } else {
     assert(RC == ARM::SPRRegisterClass && "Unknown regclass!");
-    BuildMI(MBB, I, TII.get(ARM::FSTS)).addReg(SrcReg)
+    BuildMI(MBB, I, TII.get(ARM::FSTS)).addReg(SrcReg, false, false, true)
       .addFrameIndex(FI).addImm(0);
   }
 }
@@ -320,6 +328,10 @@
   return NoFramePointerElim || MF.getFrameInfo()->hasVarSizedObjects();
 }
 
+bool ARMRegisterInfo::requiresRegisterScavenging() const {
+  return EnableScavenging;
+}
+
 /// emitARMRegPlusImmediate - Emits a series of instructions to materialize
 /// a destreg = basereg + immediate in ARM code.
 static


Index: llvm/lib/Target/ARM/ARMRegisterInfo.h
diff -u llvm/lib/Target/ARM/ARMRegisterInfo.h:1.11 llvm/lib/Target/ARM/ARMRegisterInfo.h:1.12
--- llvm/lib/Target/ARM/ARMRegisterInfo.h:1.11	Wed Feb 21 16:54:50 2007
+++ llvm/lib/Target/ARM/ARMRegisterInfo.h	Thu Feb 22 19:09:11 2007
@@ -69,6 +69,8 @@
 
   BitVector getReservedRegs(const MachineFunction &MF) const;
 
+  bool requiresRegisterScavenging() const;
+
   bool hasFP(const MachineFunction &MF) const;
 
   void eliminateCallFramePseudoInstr(MachineFunction &MF,