[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelLowering.cpp

[Chris Lattner]

Changes in directory llvm/lib/Target/PowerPC:

PPCISelLowering.cpp updated: 1.249 -> 1.250
---
Log message:

Compile test/CodeGen/PowerPC/LargeAbsoluteAddr.ll to:

_test:
        lis r2, 743
        li r3, 0
        stw r3, 32751(r2)
        blr 

instead of:

_test:
        li r2, 0
        stw r2, 32751(48693248)
        blr 

Implement support for ppc64 as well, allowing it to produce better code.



---
Diffs of the changes:  (+9 -5)

 PPCISelLowering.cpp |   14 +++++++++-----
 1 files changed, 9 insertions(+), 5 deletions(-)


Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.249 llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.250
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.249	Mon Jan 29 16:58:52 2007
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp	Sat Feb 17 00:44:03 2007
@@ -743,14 +743,18 @@
       Base = DAG.getRegister(PPC::R0, CN->getValueType(0));
       return true;
     }
-    
-    // FIXME: Handle small sext constant offsets in PPC64 mode also!
-    if (CN->getValueType(0) == MVT::i32) {
+
+    // Handle 32-bit sext immediates with LIS + addr mode.
+    if (CN->getValueType(0) == MVT::i32 ||
+        (int64_t)CN->getValue() == (int)CN->getValue()) {
       int Addr = (int)CN->getValue();
       
       // Otherwise, break this down into an LIS + disp.
-      Disp =  DAG.getTargetConstant((short)Addr, MVT::i32);
-      Base = DAG.getConstant(Addr - (signed short)Addr, MVT::i32);
+      Disp = DAG.getTargetConstant((short)Addr, MVT::i32);
+      
+      Base = DAG.getTargetConstant((Addr - (signed short)Addr) >> 16, MVT::i32);
+      unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8;
+      Base = SDOperand(DAG.getTargetNode(Opc, CN->getValueType(0), Base), 0);
       return true;
     }
   }