[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp

[Chris Lattner]

Changes in directory llvm/lib/CodeGen/SelectionDAG:

ScheduleDAG.cpp updated: 1.119 -> 1.120
---
Log message:

Apply B Scott Michel's patch for PR1184: http://llvm.org/PR1184 , which improves diagnostics in an
abort case.


---
Diffs of the changes:  (+16 -2)

 ScheduleDAG.cpp |   18 ++++++++++++++++--
 1 files changed, 16 insertions(+), 2 deletions(-)


Index: llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp:1.119 llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp:1.120
--- llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp:1.119	Wed Feb 14 21:39:18 2007
+++ llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp	Thu Feb 15 12:17:56 2007
@@ -302,8 +302,22 @@
       const TargetRegisterClass *RC =
                           getInstrOperandRegClass(MRI, TII, II, IIOpNum);
       assert(RC && "Don't have operand info for this instruction!");
-      assert(RegMap->getRegClass(VReg) == RC &&
-             "Register class of operand and regclass of use don't agree!");
+      const TargetRegisterClass *VRC = RegMap->getRegClass(VReg);
+      if (VRC != RC) {
+        cerr << "Register class of operand and regclass of use don't agree!\n";
+#ifndef NDEBUG
+        cerr << "Operand = " << IIOpNum << "\n";
+        cerr << "Op->Val = "; Op.Val->dump(0); cerr << "\n";
+        cerr << "MI = "; MI->print(cerr);
+        cerr << "VReg = " << VReg << "\n";
+        cerr << "VReg RegClass     size = " << VRC->getSize()
+          << ", align = " << VRC->getAlignment() << "\n";
+        cerr << "Expected RegClass size = " << RC->getSize()
+          << ", align = " << RC->getAlignment() << "\n";
+#endif
+        cerr << "Fatal error, aborting.\n";
+        abort();
+      }
     }
   } else if (ConstantSDNode *C =
              dyn_cast<ConstantSDNode>(Op)) {