[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp ScheduleDAGSimple.cpp

[Chris Lattner]

Changes in directory llvm/lib/CodeGen/SelectionDAG:

ScheduleDAG.cpp updated: 1.117 -> 1.118
ScheduleDAGSimple.cpp updated: 1.24 -> 1.25
---
Log message:

switch the VRBaseMap in the scheduler from an std::map to a DenseMap.  This 
speeds up the isel pass from 2.5570s to 2.4722s on kc++ (3.4%).


---
Diffs of the changes:  (+6 -6)

 ScheduleDAG.cpp       |   10 +++++-----
 ScheduleDAGSimple.cpp |    2 +-
 2 files changed, 6 insertions(+), 6 deletions(-)


Index: llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp:1.117 llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp:1.118
--- llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp:1.117	Fri Jan 26 08:34:51 2007
+++ llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp	Sun Feb  4 02:47:20 2007
@@ -269,8 +269,8 @@
 
 /// getVR - Return the virtual register corresponding to the specified result
 /// of the specified node.
-static unsigned getVR(SDOperand Op, std::map<SDNode*, unsigned> &VRBaseMap) {
-  std::map<SDNode*, unsigned>::iterator I = VRBaseMap.find(Op.Val);
+static unsigned getVR(SDOperand Op, DenseMap<SDNode*, unsigned> &VRBaseMap) {
+  DenseMap<SDNode*, unsigned>::iterator I = VRBaseMap.find(Op.Val);
   assert(I != VRBaseMap.end() && "Node emitted out of order - late");
   return I->second + Op.ResNo;
 }
@@ -283,7 +283,7 @@
 void ScheduleDAG::AddOperand(MachineInstr *MI, SDOperand Op,
                              unsigned IIOpNum,
                              const TargetInstrDescriptor *II,
-                             std::map<SDNode*, unsigned> &VRBaseMap) {
+                             DenseMap<SDNode*, unsigned> &VRBaseMap) {
   if (Op.isTargetOpcode()) {
     // Note that this case is redundant with the final else block, but we
     // include it because it is the most common and it makes the logic
@@ -371,7 +371,7 @@
 /// EmitNode - Generate machine code for an node and needed dependencies.
 ///
 void ScheduleDAG::EmitNode(SDNode *Node, 
-                           std::map<SDNode*, unsigned> &VRBaseMap) {
+                           DenseMap<SDNode*, unsigned> &VRBaseMap) {
   unsigned VRBase = 0;                 // First virtual register for node
   
   // If machine instruction
@@ -595,7 +595,7 @@
   
   
   // Finally, emit the code for all of the scheduled instructions.
-  std::map<SDNode*, unsigned> VRBaseMap;
+  DenseMap<SDNode*, unsigned> VRBaseMap;
   for (unsigned i = 0, e = Sequence.size(); i != e; i++) {
     if (SUnit *SU = Sequence[i]) {
       for (unsigned j = 0, ee = SU->FlaggedNodes.size(); j != ee; j++)


Index: llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSimple.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSimple.cpp:1.24 llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSimple.cpp:1.25
--- llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSimple.cpp:1.24	Wed Jan 31 22:55:59 2007
+++ llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSimple.cpp	Sun Feb  4 02:47:20 2007
@@ -682,7 +682,7 @@
                           LI->first, RegMap->getRegClass(LI->second));
   }
   
-  std::map<SDNode*, unsigned> VRBaseMap;
+  DenseMap<SDNode*, unsigned> VRBaseMap;
   
   // For each node in the ordering
   for (unsigned i = 0, N = Ordering.size(); i < N; i++) {