[llvm-commits] CVS: llvm/lib/Target/CBackend/CBackend.cpp

Reid Spencer reid at x10sys.com
Thu Feb 1 18:17:35 PST 2007



Changes in directory llvm/lib/Target/CBackend:

CBackend.cpp updated: 1.323 -> 1.324
---
Log message:

Changes to support making the shift instructions be true BinaryOperators.
This feature is needed in order to support shifts of more than 255 bits
on large integer types.  This changes the syntax for llvm assembly to 
make shl, ashr and lshr instructions look like a binary operator:
   shl i32 %X, 1
instead of
   shl i32 %X, i8 1
Additionally, this should help a few passes perform additional optimizations.


---
Diffs of the changes:  (+8 -9)

 CBackend.cpp |   17 ++++++++---------
 1 files changed, 8 insertions(+), 9 deletions(-)


Index: llvm/lib/Target/CBackend/CBackend.cpp
diff -u llvm/lib/Target/CBackend/CBackend.cpp:1.323 llvm/lib/Target/CBackend/CBackend.cpp:1.324
--- llvm/lib/Target/CBackend/CBackend.cpp:1.323	Tue Jan 30 14:08:37 2007
+++ llvm/lib/Target/CBackend/CBackend.cpp	Thu Feb  1 20:16:22 2007
@@ -225,7 +225,6 @@
     void visitSelectInst(SelectInst &I);
     void visitCallInst (CallInst &I);
     void visitInlineAsm(CallInst &I);
-    void visitShiftInst(ShiftInst &I) { visitBinaryOperator(I); }
 
     void visitMallocInst(MallocInst &I);
     void visitAllocaInst(AllocaInst &I);
@@ -2160,18 +2159,18 @@
     writeOperandWithCast(I.getOperand(0), I.getOpcode());
 
     switch (I.getOpcode()) {
-    case Instruction::Add: Out << " + "; break;
-    case Instruction::Sub: Out << " - "; break;
-    case Instruction::Mul: Out << '*'; break;
+    case Instruction::Add:  Out << " + "; break;
+    case Instruction::Sub:  Out << " - "; break;
+    case Instruction::Mul:  Out << " * "; break;
     case Instruction::URem:
     case Instruction::SRem:
-    case Instruction::FRem: Out << '%'; break;
+    case Instruction::FRem: Out << " % "; break;
     case Instruction::UDiv:
     case Instruction::SDiv: 
-    case Instruction::FDiv: Out << '/'; break;
-    case Instruction::And: Out << " & "; break;
-    case Instruction::Or: Out << " | "; break;
-    case Instruction::Xor: Out << " ^ "; break;
+    case Instruction::FDiv: Out << " / "; break;
+    case Instruction::And:  Out << " & "; break;
+    case Instruction::Or:   Out << " | "; break;
+    case Instruction::Xor:  Out << " ^ "; break;
     case Instruction::Shl : Out << " << "; break;
     case Instruction::LShr:
     case Instruction::AShr: Out << " >> "; break;






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