[llvm-commits] CVS: llvm/lib/Target/ARM/ARMInstrThumb.td ARMRegisterInfo.cpp

[Evan Cheng]

Changes in directory llvm/lib/Target/ARM:

ARMInstrThumb.td updated: 1.4 -> 1.5
ARMRegisterInfo.cpp updated: 1.41 -> 1.42
---
Log message:

Represent tADDspi and tSUBspi as two-address instructions.

---
Diffs of the changes:  (+5 -5)

 ARMInstrThumb.td    |    8 ++++----
 ARMRegisterInfo.cpp |    2 +-
 2 files changed, 5 insertions(+), 5 deletions(-)


Index: llvm/lib/Target/ARM/ARMInstrThumb.td
diff -u llvm/lib/Target/ARM/ARMInstrThumb.td:1.4 llvm/lib/Target/ARM/ARMInstrThumb.td:1.5
--- llvm/lib/Target/ARM/ARMInstrThumb.td:1.4	Fri Jan 26 13:13:16 2007
+++ llvm/lib/Target/ARM/ARMInstrThumb.td	Fri Jan 26 15:33:19 2007
@@ -285,8 +285,8 @@
                   "add $dst, pc, $rhs * 4", []>;
 def tADDrSPi : TI<(ops GPR:$dst, GPR:$sp, i32imm:$rhs),
                   "add $dst, $sp, $rhs * 4", []>;
-def tADDspi : TI<(ops GPR:$sp, i32imm:$rhs),
-                 "add $sp, $rhs * 4", []>;
+def tADDspi : TIt<(ops GPR:$dst, GPR:$lhs, i32imm:$rhs),
+                  "add $dst, $rhs * 4", []>;
 
 
 def tAND : TIt<(ops GPR:$dst, GPR:$lhs, GPR:$rhs),
@@ -413,8 +413,8 @@
                 "sub $dst, $lhs, $rhs",
                 [(set GPR:$dst, (sub GPR:$lhs, GPR:$rhs))]>;
 
-def tSUBspi : TI<(ops GPR:$sp, i32imm:$rhs),
-                 "sub $sp, $rhs * 4", []>;
+def tSUBspi : TIt<(ops GPR:$dst, GPR:$lhs, i32imm:$rhs),
+                  "sub $dst, $rhs * 4", []>;
 
 def tSXTB  : TI<(ops GPR:$dst, GPR:$src),
                 "sxtb $dst, $src",


Index: llvm/lib/Target/ARM/ARMRegisterInfo.cpp
diff -u llvm/lib/Target/ARM/ARMRegisterInfo.cpp:1.41 llvm/lib/Target/ARM/ARMRegisterInfo.cpp:1.42
--- llvm/lib/Target/ARM/ARMRegisterInfo.cpp:1.41	Thu Jan 25 17:18:16 2007
+++ llvm/lib/Target/ARM/ARMRegisterInfo.cpp	Fri Jan 26 15:33:19 2007
@@ -378,7 +378,7 @@
     Bytes -= ThisVal;    
     // Build the new tADD / tSUB.
     if (isTwoAddr)
-      BuildMI(MBB, MBBI, TII.get(Opc), DestReg).addImm(ThisVal);
+      BuildMI(MBB, MBBI, TII.get(Opc), DestReg).addReg(DestReg).addImm(ThisVal);
     else {
       BuildMI(MBB, MBBI, TII.get(Opc), DestReg).addReg(BaseReg).addImm(ThisVal);
       BaseReg = DestReg;