[llvm-commits] [patch] Intruction Constraint DestReg!=SrcReg (for review)

[Lauro Ramos Venancio]

Hi Evan,

Tanks for your review.

> 1. I think rather than adding a constraint that says a source operand
> must not be assigned the same register as another. It would be better
> if you add a constraint that says a source operand "can be killed at
> issue cycle + n". The live range analysis current assumes every
> source operand read is completed at issue cycle + 0 and write back
> happens at issue cycle + 2. By changing the read latency to 2 you can
> force a source operand to conflict with a destination operand.

Currently, kill moment of a temporary is determined by the last use of
it. With the constraint proposed by you, an intermediary use could
determine kill moment of a temporary. For example, in an use (with
read latency 5) of a temporary followed by other use of it (with read
latency 0), the kill moment would be determined by first use. This
would complicate liveness algorithm. Does any backend need this
constraint?

Maybe, it would be better a constraint that changes the kill moment
from default (can kill at issue cycle + 0) to "can kill after
instruction execution". What do you think?

Lauro