[llvm-commits] [patch] Intruction Constraint DestReg!=SrcReg (for review)
Lauro Ramos Venancio
lauro.venancio at gmail.com
Thu Jan 25 13:54:38 PST 2007
This patch implements the instruction constraint DestReg!=SrcReg. It
is needed by ARM backend.
A sample of use of this constraint is following:
class RegConstraint<string C> {
string Constraints = C;
}
// AI_orr - Defines a (op r, r) pattern.
class AI_orr<string opc, SDNode opnode>
: AI<(ops GPR:$dst, GPR:$a, GPR:$b),
!strconcat(opc, " $dst, $a, $b"),
[(set GPR:$dst, (opnode GPR:$a, GPR:$b))]>,
RegConstraint<"$dst != $a">;
Lauro
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