[llvm-commits] CVS: llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp AlphaISelLowering.cpp AlphaISelLowering.h

[Reid Spencer]

Changes in directory llvm/lib/Target/Alpha:

AlphaISelDAGToDAG.cpp updated: 1.64 -> 1.65
AlphaISelLowering.cpp updated: 1.75 -> 1.76
AlphaISelLowering.h updated: 1.22 -> 1.23
---
Log message:

For PR950: http://llvm.org/PR950 :
Three changes:
1. Convert signed integer types to signless versions.
2. Implement the @sext and @zext parameter attributes. Previously the
   type of an function parameter was used to determine whether it should
   be sign extended or zero extended before the call. This information is
   now communicated via the function type's parameter attributes. 
3. The interface to LowerCallTo had to be changed in order to accommodate
   the parameter attribute information. Although it would have been
   convenient to pass in the FunctionType itself, there isn't always one
   present in the caller. Consequently, a signedness indication for the
   result type and for each parameter was provided for in the interface
   to this method. All implementations were changed to make the adjustment
   necessary.


---
Diffs of the changes:  (+12 -12)

 AlphaISelDAGToDAG.cpp |    2 +-
 AlphaISelLowering.cpp |   16 ++++++++--------
 AlphaISelLowering.h   |    6 +++---
 3 files changed, 12 insertions(+), 12 deletions(-)


Index: llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp
diff -u llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp:1.64 llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp:1.65
--- llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp:1.64	Tue Dec 19 16:59:25 2006
+++ llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp	Sat Dec 30 23:55:36 2006
@@ -322,7 +322,7 @@
       //	val32 >= IMM_LOW  + IMM_LOW  * IMM_MULT) //always true
       break; //(zext (LDAH (LDA)))
     //Else use the constant pool
-    ConstantInt *C = ConstantInt::get(Type::ULongTy, uval);
+    ConstantInt *C = ConstantInt::get(Type::Int64Ty, uval);
     SDOperand CPI = CurDAG->getTargetConstantPool(C, MVT::i64);
     SDNode *Tmp = CurDAG->getTargetNode(Alpha::LDAHr, MVT::i64, CPI,
                                         getGlobalBaseReg());


Index: llvm/lib/Target/Alpha/AlphaISelLowering.cpp
diff -u llvm/lib/Target/Alpha/AlphaISelLowering.cpp:1.75 llvm/lib/Target/Alpha/AlphaISelLowering.cpp:1.76
--- llvm/lib/Target/Alpha/AlphaISelLowering.cpp:1.75	Thu Dec  7 16:21:48 2006
+++ llvm/lib/Target/Alpha/AlphaISelLowering.cpp	Sat Dec 30 23:55:36 2006
@@ -317,8 +317,8 @@
 }
 
 std::pair<SDOperand, SDOperand>
-AlphaTargetLowering::LowerCallTo(SDOperand Chain,
-                                 const Type *RetTy, bool isVarArg,
+AlphaTargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy, 
+                                 bool RetTyIsSigned, bool isVarArg,
                                  unsigned CallingConv, bool isTailCall,
                                  SDOperand Callee, ArgListTy &Args,
                                  SelectionDAG &DAG) {
@@ -331,7 +331,7 @@
   std::vector<SDOperand> args_to_use;
   for (unsigned i = 0, e = Args.size(); i != e; ++i)
   {
-    switch (getValueType(Args[i].second)) {
+    switch (getValueType(Args[i].Ty)) {
     default: assert(0 && "Unexpected ValueType for argument!");
     case MVT::i1:
     case MVT::i8:
@@ -339,17 +339,17 @@
     case MVT::i32:
       // Promote the integer to 64 bits.  If the input type is signed use a
       // sign extend, otherwise use a zero extend.
-      if (Args[i].second->isSigned())
-        Args[i].first = DAG.getNode(ISD::SIGN_EXTEND, MVT::i64, Args[i].first);
+      if (Args[i].isSigned)
+        Args[i].Node = DAG.getNode(ISD::SIGN_EXTEND, MVT::i64, Args[i].Node);
       else
-        Args[i].first = DAG.getNode(ISD::ZERO_EXTEND, MVT::i64, Args[i].first);
+        Args[i].Node = DAG.getNode(ISD::ZERO_EXTEND, MVT::i64, Args[i].Node);
       break;
     case MVT::i64:
     case MVT::f64:
     case MVT::f32:
       break;
     }
-    args_to_use.push_back(Args[i].first);
+    args_to_use.push_back(Args[i].Node);
   }
 
   std::vector<MVT::ValueType> RetVals;
@@ -373,7 +373,7 @@
   SDOperand RetVal = TheCall;
 
   if (RetTyVT != ActualRetTyVT) {
-    RetVal = DAG.getNode(RetTy->isSigned() ? ISD::AssertSext : ISD::AssertZext,
+    RetVal = DAG.getNode(RetTyIsSigned ? ISD::AssertSext : ISD::AssertZext,
                          MVT::i64, RetVal, DAG.getValueType(RetTyVT));
     RetVal = DAG.getNode(ISD::TRUNCATE, RetTyVT, RetVal);
   }


Index: llvm/lib/Target/Alpha/AlphaISelLowering.h
diff -u llvm/lib/Target/Alpha/AlphaISelLowering.h:1.22 llvm/lib/Target/Alpha/AlphaISelLowering.h:1.23
--- llvm/lib/Target/Alpha/AlphaISelLowering.h:1.22	Tue Oct 31 10:49:55 2006
+++ llvm/lib/Target/Alpha/AlphaISelLowering.h	Sat Dec 30 23:55:36 2006
@@ -77,9 +77,9 @@
     /// LowerCallTo - This hook lowers an abstract call to a function into an
     /// actual call.
     virtual std::pair<SDOperand, SDOperand>
-    LowerCallTo(SDOperand Chain, const Type *RetTy, bool isVarArg, unsigned CC,
-                bool isTailCall, SDOperand Callee, ArgListTy &Args,
-                SelectionDAG &DAG);
+    LowerCallTo(SDOperand Chain, const Type *RetTy, bool RetTyIsSigned, 
+                bool isVarArg, unsigned CC, bool isTailCall, SDOperand Callee, 
+                ArgListTy &Args, SelectionDAG &DAG);
 
     ConstraintType getConstraintType(char ConstraintLetter) const;