[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp

[Evan Cheng]

Changes in directory llvm/lib/CodeGen/SelectionDAG:

SelectionDAGISel.cpp updated: 1.328 -> 1.329
---
Log message:

Expand i32/i64 CopyToReg f32/f64 to BIT_CONVERT + CopyToReg.

---
Diffs of the changes:  (+3 -0)

 SelectionDAGISel.cpp |    3 +++
 1 files changed, 3 insertions(+)


Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.328 llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.329
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.328	Tue Dec 12 01:27:38 2006
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp	Tue Dec 12 15:21:32 2006
@@ -3942,6 +3942,9 @@
     else
       Op = DAG.getNode(ISD::ANY_EXTEND, DestVT, Op);
     return DAG.getCopyToReg(getRoot(), Reg, Op);
+  } else if (SrcVT == MVT::f32 || SrcVT == MVT::f64) {
+    return DAG.getCopyToReg(getRoot(), Reg,
+                            DAG.getNode(ISD::BIT_CONVERT, DestVT, Op));
   } else  {
     // The src value is expanded into multiple registers.
     SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DestVT,