[llvm-commits] CVS: llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp ARMInstrInfo.td

[Rafael Espindola]

Changes in directory llvm/lib/Target/ARM:

ARMISelDAGToDAG.cpp updated: 1.90 -> 1.91
ARMInstrInfo.td updated: 1.78 -> 1.79
---
Log message:

more general matching of the MVN instruction


---
Diffs of the changes:  (+11 -37)

 ARMISelDAGToDAG.cpp |   37 +++++++++++--------------------------
 ARMInstrInfo.td     |   11 -----------
 2 files changed, 11 insertions(+), 37 deletions(-)


Index: llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
diff -u llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp:1.90 llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp:1.91
--- llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp:1.90	Tue Dec 12 08:03:29 2006
+++ llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp	Tue Dec 12 11:10:13 2006
@@ -849,13 +849,17 @@
   case ISD::Constant: {
     uint32_t val = cast<ConstantSDNode>(N)->getValue();
     if(!isRotInt8Immediate(val)) {
-      if (isRotInt8Immediate(~val))
-        return false; //use MVN
-      Constant    *C = ConstantInt::get(Type::UIntTy, val);
-      int  alignment = 2;
-      SDOperand Addr = CurDAG->getTargetConstantPool(C, MVT::i32, alignment);
-      SDOperand    Z = CurDAG->getTargetConstant(0,     MVT::i32);
-      SDNode      *n = CurDAG->getTargetNode(ARM::LDR,  MVT::i32, Addr, Z);
+      SDOperand Z = CurDAG->getTargetConstant(0,     MVT::i32);
+      SDNode *n;
+      if (isRotInt8Immediate(~val)) {
+        SDOperand C = CurDAG->getTargetConstant(~val,  MVT::i32);
+        n           = CurDAG->getTargetNode(ARM::MVN,  MVT::i32, C, Z, Z);
+     } else {
+        Constant    *C = ConstantInt::get(Type::UIntTy, val);
+        int  alignment = 2;
+        SDOperand Addr = CurDAG->getTargetConstantPool(C, MVT::i32, alignment);
+        n              = CurDAG->getTargetNode(ARM::LDR,  MVT::i32, Addr, Z);
+      }
       Arg            = SDOperand(n, 0);
     } else
       Arg            = CurDAG->getTargetConstant(val,    MVT::i32);
@@ -887,25 +891,6 @@
   return true;
 }
 
-bool ARMDAGToDAGISel::SelectAddrMode1a(SDOperand Op,
-				       SDOperand N,
-				       SDOperand &Arg,
-				       SDOperand &Shift,
-				       SDOperand &ShiftType) {
-  if (N.getOpcode() != ISD::Constant)
-    return false;
-
-  uint32_t val = ~cast<ConstantSDNode>(N)->getValue();
-  if(!isRotInt8Immediate(val))
-    return false;
-
-  Arg       = CurDAG->getTargetConstant(val,    MVT::i32);
-  Shift     = CurDAG->getTargetConstant(0,             MVT::i32);
-  ShiftType = CurDAG->getTargetConstant(ARMShift::LSL, MVT::i32);
-
-  return true;
-}
-
 bool ARMDAGToDAGISel::SelectAddrMode2(SDOperand Op, SDOperand N,
                                       SDOperand &Arg, SDOperand &Offset) {
   //TODO: complete and cleanup!


Index: llvm/lib/Target/ARM/ARMInstrInfo.td
diff -u llvm/lib/Target/ARM/ARMInstrInfo.td:1.78 llvm/lib/Target/ARM/ARMInstrInfo.td:1.79
--- llvm/lib/Target/ARM/ARMInstrInfo.td:1.78	Mon Dec 11 19:03:11 2006
+++ llvm/lib/Target/ARM/ARMInstrInfo.td	Tue Dec 12 11:10:13 2006
@@ -18,11 +18,6 @@
   let MIOperandInfo = (ops ptr_rc, ptr_rc, i32imm);
 }
 
-def op_addr_mode1a : Operand<iPTR> {
-  let PrintMethod = "printAddrMode1";
-  let MIOperandInfo = (ops ptr_rc, ptr_rc, i32imm);
-}
-
 def op_addr_mode2 : Operand<iPTR> {
   let PrintMethod = "printAddrMode2";
   let MIOperandInfo = (ops ptr_rc, i32imm);
@@ -38,9 +33,6 @@
 def addr_mode1 : ComplexPattern<iPTR, 3, "SelectAddrMode1", [imm, sra, shl, srl],
                                 []>;
 
-//Addressing Mode 1a: MVN hack
-def addr_mode1a : ComplexPattern<iPTR, 3, "SelectAddrMode1a", [imm], []>;
-
 //Addressing Mode 2: Load and Store Word or Unsigned Byte
 def addr_mode2 : ComplexPattern<iPTR, 2, "SelectAddrMode2", [], []>;
 
@@ -201,9 +193,6 @@
 def MVN     : InstARM<(ops IntRegs:$dst, op_addr_mode1:$src),
                        "mvn $dst, $src", [(set IntRegs:$dst, (not addr_mode1:$src))]>;
 
-def MVN2    : InstARM<(ops IntRegs:$dst, op_addr_mode1:$src),
-                       "mvn $dst, $src", [(set IntRegs:$dst, addr_mode1a:$src)]>;
-
 def ADD     : Addr1BinOp<"add",  add>;
 def ADCS    : Addr1BinOp<"adcs", adde>;
 def ADDS    : Addr1BinOp<"adds", addc>;