[llvm-commits] CVS: llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp

[Rafael Espindola]

Changes in directory llvm/lib/Target/ARM:

ARMISelDAGToDAG.cpp updated: 1.85 -> 1.86
---
Log message:

add support for the "r" asm constraint
patch by Lauro Ramos Venancio


---
Diffs of the changes:  (+27 -0)

 ARMISelDAGToDAG.cpp |   27 +++++++++++++++++++++++++++
 1 files changed, 27 insertions(+)


Index: llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
diff -u llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp:1.85 llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp:1.86
--- llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp:1.85	Thu Nov  9 07:58:55 2006
+++ llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp	Tue Dec  5 11:37:31 2006
@@ -18,6 +18,7 @@
 #include "llvm/Function.h"
 #include "llvm/Constants.h"
 #include "llvm/Intrinsics.h"
+#include "llvm/ADT/VectorExtras.h"
 #include "llvm/CodeGen/MachineFrameInfo.h"
 #include "llvm/CodeGen/MachineFunction.h"
 #include "llvm/CodeGen/MachineInstrBuilder.h"
@@ -37,6 +38,9 @@
     ARMTargetLowering(TargetMachine &TM);
     virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG);
     virtual const char *getTargetNodeName(unsigned Opcode) const;
+    std::vector<unsigned>
+    getRegClassForInlineAsmConstraint(const std::string &Constraint,
+				      MVT::ValueType VT) const;
   };
 
 }
@@ -200,6 +204,29 @@
   }
 }
 
+std::vector<unsigned> ARMTargetLowering::
+getRegClassForInlineAsmConstraint(const std::string &Constraint,
+                                  MVT::ValueType VT) const {
+  if (Constraint.size() == 1) {
+    // FIXME: handling only r regs
+    switch (Constraint[0]) {
+    default: break;  // Unknown constraint letter
+
+    case 'r':   // GENERAL_REGS
+    case 'R':   // LEGACY_REGS
+      if (VT == MVT::i32)
+        return make_vector<unsigned>(ARM::R0,  ARM::R1,  ARM::R2,  ARM::R3,
+                                     ARM::R4,  ARM::R5,  ARM::R6,  ARM::R7,
+                                     ARM::R8,  ARM::R9,  ARM::R10, ARM::R11,
+                                     ARM::R12, ARM::R13, ARM::R14, 0);
+      break;
+
+    }
+  }
+
+  return std::vector<unsigned>();
+}
+
 const char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const {
   switch (Opcode) {
   default: return 0;