[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp X86InstrInfo.td

[Evan Cheng]

Changes in directory llvm/lib/Target/X86:

X86ISelLowering.cpp updated: 1.295 -> 1.296
X86InstrInfo.td updated: 1.294 -> 1.295
---
Log message:

Custom lower READCYCLECOUNTER for x86-64.

---
Diffs of the changes:  (+22 -12)

 X86ISelLowering.cpp |   26 ++++++++++++++++++++------
 X86InstrInfo.td     |    8 ++------
 2 files changed, 22 insertions(+), 12 deletions(-)


Index: llvm/lib/Target/X86/X86ISelLowering.cpp
diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.295 llvm/lib/Target/X86/X86ISelLowering.cpp:1.296
--- llvm/lib/Target/X86/X86ISelLowering.cpp:1.295	Mon Nov 27 17:37:22 2006
+++ llvm/lib/Target/X86/X86ISelLowering.cpp	Wed Nov 29 02:28:13 2006
@@ -4728,12 +4728,26 @@
   Ops.push_back(Op.getOperand(0));
   SDOperand rd = DAG.getNode(X86ISD::RDTSC_DAG, Tys, &Ops[0], Ops.size());
   Ops.clear();
-  Ops.push_back(DAG.getCopyFromReg(rd, X86::EAX, MVT::i32, rd.getValue(1)));
-  Ops.push_back(DAG.getCopyFromReg(Ops[0].getValue(1), X86::EDX,
-                                   MVT::i32, Ops[0].getValue(2)));
-  Ops.push_back(Ops[1].getValue(1));
-  Tys[0] = Tys[1] = MVT::i32;
-  Tys.push_back(MVT::Other);
+  if (Subtarget->is64Bit()) {
+    SDOperand Copy1 = DAG.getCopyFromReg(rd, X86::RAX, MVT::i64, rd.getValue(1));
+    SDOperand Copy2 = DAG.getCopyFromReg(Copy1.getValue(1), X86::RDX,
+                                         MVT::i64, Copy1.getValue(2));
+    SDOperand Tmp = DAG.getNode(ISD::SHL, MVT::i64, Copy2,
+                                DAG.getConstant(32, MVT::i8));
+    Ops.push_back(DAG.getNode(ISD::OR, MVT::i64, Copy1, Tmp));
+    Ops.push_back(Copy2.getValue(1));
+    Tys[0] = MVT::i64;
+    Tys[1] = MVT::Other;
+  } else {
+    SDOperand Copy1 = DAG.getCopyFromReg(rd, X86::EAX, MVT::i32, rd.getValue(1));
+    SDOperand Copy2 = DAG.getCopyFromReg(Copy1.getValue(1), X86::EDX,
+                                         MVT::i32, Copy1.getValue(2));
+    Ops.push_back(Copy1);
+    Ops.push_back(Copy2);
+    Ops.push_back(Copy2.getValue(1));
+    Tys[0] = Tys[1] = MVT::i32;
+    Tys.push_back(MVT::Other);
+  }
   return DAG.getNode(ISD::MERGE_VALUES, Tys, &Ops[0], Ops.size());
 }
 


Index: llvm/lib/Target/X86/X86InstrInfo.td
diff -u llvm/lib/Target/X86/X86InstrInfo.td:1.294 llvm/lib/Target/X86/X86InstrInfo.td:1.295
--- llvm/lib/Target/X86/X86InstrInfo.td:1.294	Fri Nov  3 17:48:55 2006
+++ llvm/lib/Target/X86/X86InstrInfo.td	Wed Nov 29 02:28:13 2006
@@ -536,6 +536,8 @@
                   [(X86rep_stos i32)]>,
                 Imp<[EAX,ECX,EDI], [ECX,EDI]>, REP;
 
+def RDTSC : I<0x31, RawFrm, (ops), "rdtsc", [(X86rdtsc)]>,
+            TB, Imp<[],[RAX,RDX]>;
 
 //===----------------------------------------------------------------------===//
 //  Input/Output Instructions...
@@ -2397,12 +2399,6 @@
 def CDQ : I<0x99, RawFrm, (ops),
             "{cltd|cdq}", []>, Imp<[EAX],[EAX,EDX]>; // EDX:EAX = signext(EAX)
           
-//===----------------------------------------------------------------------===//
-// Miscellaneous Instructions
-//===----------------------------------------------------------------------===//
-
-def RDTSC : I<0x31, RawFrm, (ops), "rdtsc", [(X86rdtsc)]>,
-            TB, Imp<[],[EAX,EDX]>;
 
 //===----------------------------------------------------------------------===//
 // Alias Instructions