[llvm-commits] CVS: llvm/lib/Target/ARM/ARMInstrInfo.cpp ARMMul.cpp ARMRegisterInfo.cpp ARMRegisterInfo.h
Evan Cheng
evan.cheng at apple.com
Mon Nov 27 15:37:45 PST 2006
Changes in directory llvm/lib/Target/ARM:
ARMInstrInfo.cpp updated: 1.9 -> 1.10
ARMMul.cpp updated: 1.3 -> 1.4
ARMRegisterInfo.cpp updated: 1.26 -> 1.27
ARMRegisterInfo.h updated: 1.2 -> 1.3
---
Log message:
Change MachineInstr ctor's to take a TargetInstrDescriptor reference instead
of opcode and number of operands.
---
Diffs of the changes: (+28 -21)
ARMInstrInfo.cpp | 5 +++--
ARMMul.cpp | 6 ++++--
ARMRegisterInfo.cpp | 34 ++++++++++++++++++----------------
ARMRegisterInfo.h | 4 +++-
4 files changed, 28 insertions(+), 21 deletions(-)
Index: llvm/lib/Target/ARM/ARMInstrInfo.cpp
diff -u llvm/lib/Target/ARM/ARMInstrInfo.cpp:1.9 llvm/lib/Target/ARM/ARMInstrInfo.cpp:1.10
--- llvm/lib/Target/ARM/ARMInstrInfo.cpp:1.9 Tue Oct 24 12:07:11 2006
+++ llvm/lib/Target/ARM/ARMInstrInfo.cpp Mon Nov 27 17:37:22 2006
@@ -19,7 +19,8 @@
using namespace llvm;
ARMInstrInfo::ARMInstrInfo()
- : TargetInstrInfo(ARMInsts, sizeof(ARMInsts)/sizeof(ARMInsts[0])) {
+ : TargetInstrInfo(ARMInsts, sizeof(ARMInsts)/sizeof(ARMInsts[0])),
+ RI(*this) {
}
const TargetRegisterClass *ARMInstrInfo::getPointerRegClass() const {
@@ -54,5 +55,5 @@
const std::vector<MachineOperand> &Cond)const{
// Can only insert uncond branches so far.
assert(Cond.empty() && !FBB && TBB && "Can only handle uncond branches!");
- BuildMI(&MBB, ARM::b, 1).addMBB(TBB);
+ BuildMI(&MBB, get(ARM::b)).addMBB(TBB);
}
Index: llvm/lib/Target/ARM/ARMMul.cpp
diff -u llvm/lib/Target/ARM/ARMMul.cpp:1.3 llvm/lib/Target/ARM/ARMMul.cpp:1.4
--- llvm/lib/Target/ARM/ARMMul.cpp:1.3 Mon Oct 16 11:33:29 2006
+++ llvm/lib/Target/ARM/ARMMul.cpp Mon Nov 27 17:37:22 2006
@@ -16,6 +16,8 @@
#include "ARM.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
+#include "llvm/Target/TargetMachine.h"
+#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Support/Compiler.h"
using namespace llvm;
@@ -60,8 +62,8 @@
RsOp.setReg(Rm);
} else {
unsigned scratch = Op == ARM::MUL ? ARM::R12 : ARM::R0;
- BuildMI(MBB, I, ARM::MOV, 3, scratch).addReg(Rm).addImm(0)
- .addImm(ARMShift::LSL);
+ BuildMI(MBB, I, MF.getTarget().getInstrInfo()->get(ARM::MOV),
+ scratch).addReg(Rm).addImm(0).addImm(ARMShift::LSL);
RmOp.setReg(scratch);
}
}
Index: llvm/lib/Target/ARM/ARMRegisterInfo.cpp
diff -u llvm/lib/Target/ARM/ARMRegisterInfo.cpp:1.26 llvm/lib/Target/ARM/ARMRegisterInfo.cpp:1.27
--- llvm/lib/Target/ARM/ARMRegisterInfo.cpp:1.26 Thu Nov 9 07:58:55 2006
+++ llvm/lib/Target/ARM/ARMRegisterInfo.cpp Mon Nov 27 17:37:22 2006
@@ -22,6 +22,7 @@
#include "llvm/Target/TargetFrameInfo.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetOptions.h"
+#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/ADT/STLExtras.h"
#include <iostream>
using namespace llvm;
@@ -35,8 +36,9 @@
return NoFramePointerElim || MFI->hasVarSizedObjects();
}
-ARMRegisterInfo::ARMRegisterInfo()
- : ARMGenRegisterInfo(ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP) {
+ARMRegisterInfo::ARMRegisterInfo(const TargetInstrInfo &tii)
+ : ARMGenRegisterInfo(ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP),
+ TII(tii) {
}
void ARMRegisterInfo::
@@ -44,7 +46,7 @@
unsigned SrcReg, int FI,
const TargetRegisterClass *RC) const {
assert (RC == ARM::IntRegsRegisterClass);
- BuildMI(MBB, I, ARM::STR, 3).addReg(SrcReg).addFrameIndex(FI).addImm(0);
+ BuildMI(MBB, I, TII.get(ARM::STR)).addReg(SrcReg).addFrameIndex(FI).addImm(0);
}
void ARMRegisterInfo::
@@ -52,7 +54,7 @@
unsigned DestReg, int FI,
const TargetRegisterClass *RC) const {
assert (RC == ARM::IntRegsRegisterClass);
- BuildMI(MBB, I, ARM::LDR, 2, DestReg).addFrameIndex(FI).addImm(0);
+ BuildMI(MBB, I, TII.get(ARM::LDR), DestReg).addFrameIndex(FI).addImm(0);
}
void ARMRegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
@@ -64,12 +66,12 @@
RC == ARM::DFPRegsRegisterClass);
if (RC == ARM::IntRegsRegisterClass)
- BuildMI(MBB, I, ARM::MOV, 3, DestReg).addReg(SrcReg).addImm(0)
+ BuildMI(MBB, I, TII.get(ARM::MOV), DestReg).addReg(SrcReg).addImm(0)
.addImm(ARMShift::LSL);
else if (RC == ARM::FPRegsRegisterClass)
- BuildMI(MBB, I, ARM::FCPYS, 1, DestReg).addReg(SrcReg);
+ BuildMI(MBB, I, TII.get(ARM::FCPYS), DestReg).addReg(SrcReg);
else
- BuildMI(MBB, I, ARM::FCPYD, 1, DestReg).addReg(SrcReg);
+ BuildMI(MBB, I, TII.get(ARM::FCPYD), DestReg).addReg(SrcReg);
}
MachineInstr *ARMRegisterInfo::foldMemoryOperand(MachineInstr* MI,
@@ -109,12 +111,12 @@
if (Old->getOpcode() == ARM::ADJCALLSTACKDOWN) {
// sub sp, sp, amount
- BuildMI(MBB, I, ARM::SUB, 2, ARM::R13).addReg(ARM::R13).addImm(Amount)
+ BuildMI(MBB, I, TII.get(ARM::SUB), ARM::R13).addReg(ARM::R13).addImm(Amount)
.addImm(0).addImm(ARMShift::LSL);
} else {
// add sp, sp, amount
assert(Old->getOpcode() == ARM::ADJCALLSTACKUP);
- BuildMI(MBB, I, ARM::ADD, 2, ARM::R13).addReg(ARM::R13).addImm(Amount)
+ BuildMI(MBB, I, TII.get(ARM::ADD), ARM::R13).addReg(ARM::R13).addImm(Amount)
.addImm(0).addImm(ARMShift::LSL);
}
}
@@ -155,7 +157,7 @@
// Insert a set of r12 with the full address
// r12 = r13 + offset
MachineBasicBlock *MBB2 = MI.getParent();
- BuildMI(*MBB2, II, ARM::ADD, 4, ARM::R12).addReg(BaseRegister)
+ BuildMI(*MBB2, II, TII.get(ARM::ADD), ARM::R12).addReg(BaseRegister)
.addImm(Offset).addImm(0).addImm(ARMShift::LSL);
// Replace the FrameIndex with r12
@@ -191,13 +193,13 @@
MFI->setStackSize(NumBytes);
//sub sp, sp, #NumBytes
- BuildMI(MBB, MBBI, ARM::SUB, 4, ARM::R13).addReg(ARM::R13).addImm(NumBytes)
+ BuildMI(MBB, MBBI, TII.get(ARM::SUB), ARM::R13).addReg(ARM::R13).addImm(NumBytes)
.addImm(0).addImm(ARMShift::LSL);
if (HasFP) {
- BuildMI(MBB, MBBI, ARM::STR, 3)
+ BuildMI(MBB, MBBI, TII.get(ARM::STR))
.addReg(ARM::R11).addReg(ARM::R13).addImm(0);
- BuildMI(MBB, MBBI, ARM::MOV, 3, ARM::R11).addReg(ARM::R13).addImm(0).
+ BuildMI(MBB, MBBI, TII.get(ARM::MOV), ARM::R11).addReg(ARM::R13).addImm(0).
addImm(ARMShift::LSL);
}
}
@@ -212,13 +214,13 @@
int NumBytes = (int) MFI->getStackSize();
if (hasFP(MF)) {
- BuildMI(MBB, MBBI, ARM::MOV, 3, ARM::R13).addReg(ARM::R11).addImm(0).
+ BuildMI(MBB, MBBI, TII.get(ARM::MOV), ARM::R13).addReg(ARM::R11).addImm(0).
addImm(ARMShift::LSL);
- BuildMI(MBB, MBBI, ARM::LDR, 2, ARM::R11).addReg(ARM::R13).addImm(0);
+ BuildMI(MBB, MBBI, TII.get(ARM::LDR), ARM::R11).addReg(ARM::R13).addImm(0);
}
//add sp, sp, #NumBytes
- BuildMI(MBB, MBBI, ARM::ADD, 4, ARM::R13).addReg(ARM::R13).addImm(NumBytes)
+ BuildMI(MBB, MBBI, TII.get(ARM::ADD), ARM::R13).addReg(ARM::R13).addImm(NumBytes)
.addImm(0).addImm(ARMShift::LSL);
}
Index: llvm/lib/Target/ARM/ARMRegisterInfo.h
diff -u llvm/lib/Target/ARM/ARMRegisterInfo.h:1.2 llvm/lib/Target/ARM/ARMRegisterInfo.h:1.3
--- llvm/lib/Target/ARM/ARMRegisterInfo.h:1.2 Wed May 17 19:11:26 2006
+++ llvm/lib/Target/ARM/ARMRegisterInfo.h Mon Nov 27 17:37:22 2006
@@ -21,10 +21,12 @@
namespace llvm {
class Type;
+class TargetInstrInfo;
struct ARMRegisterInfo : public ARMGenRegisterInfo {
+ const TargetInstrInfo &TII;
- ARMRegisterInfo();
+ ARMRegisterInfo(const TargetInstrInfo &tii);
/// Code Generation virtual methods...
void storeRegToStackSlot(MachineBasicBlock &MBB,
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