[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCBranchSelector.cpp PPCISelDAGToDAG.cpp PPCISelLowering.cpp PPCInstrInfo.cpp PPCInstrInfo.td
Chris Lattner
sabre at nondot.org
Fri Nov 17 14:37:48 PST 2006
Changes in directory llvm/lib/Target/PowerPC:
PPCBranchSelector.cpp updated: 1.36 -> 1.37
PPCISelDAGToDAG.cpp updated: 1.223 -> 1.224
PPCISelLowering.cpp updated: 1.230 -> 1.231
PPCInstrInfo.cpp updated: 1.33 -> 1.34
PPCInstrInfo.td updated: 1.268 -> 1.269
---
Log message:
convert PPC::BCC to use the 'pred' operand instead of separate predicate
value and CR reg #. This requires swapping the order of these everywhere
that touches BCC and requires us to write custom matching logic for
PPCcondbranch :(
---
Diffs of the changes: (+25 -14)
PPCBranchSelector.cpp | 4 ++--
PPCISelDAGToDAG.cpp | 12 +++++++++++-
PPCISelLowering.cpp | 4 ++--
PPCInstrInfo.cpp | 6 +++---
PPCInstrInfo.td | 13 +++++++------
5 files changed, 25 insertions(+), 14 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCBranchSelector.cpp
diff -u llvm/lib/Target/PowerPC/PPCBranchSelector.cpp:1.36 llvm/lib/Target/PowerPC/PPCBranchSelector.cpp:1.37
--- llvm/lib/Target/PowerPC/PPCBranchSelector.cpp:1.36 Fri Nov 17 16:14:47 2006
+++ llvm/lib/Target/PowerPC/PPCBranchSelector.cpp Fri Nov 17 16:37:34 2006
@@ -126,8 +126,8 @@
// 1. PPC branch opcode
// 2. Target MBB
MachineBasicBlock *DestMBB = MBBI->getOperand(2).getMachineBasicBlock();
- PPC::Predicate Pred = (PPC::Predicate)MBBI->getOperand(1).getImm();
- unsigned CRReg = MBBI->getOperand(0).getReg();
+ PPC::Predicate Pred = (PPC::Predicate)MBBI->getOperand(0).getImm();
+ unsigned CRReg = MBBI->getOperand(1).getReg();
int Displacement = OffsetMap[DestMBB->getNumber()] - ByteCount;
bool ShortBranchOk = Displacement >= -32768 && Displacement <= 32767;
Index: llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
diff -u llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:1.223 llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:1.224
--- llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:1.223 Fri Nov 17 16:14:47 2006
+++ llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp Fri Nov 17 16:37:34 2006
@@ -1001,11 +1001,21 @@
getI32Imm(BROpc) };
return CurDAG->SelectNodeTo(N, SelectCCOp, N->getValueType(0), Ops, 4);
}
+ case PPCISD::COND_BRANCH: {
+ AddToISelQueue(N->getOperand(0)); // Op #0 is the Chain.
+ // Op #1 is the PPC::PRED_* number.
+ // Op #2 is the CR#
+ // Op #3 is the Dest MBB
+ AddToISelQueue(N->getOperand(4)); // Op #4 is the Flag.
+ SDOperand Ops[] = { N->getOperand(1), N->getOperand(2), N->getOperand(3),
+ N->getOperand(0), N->getOperand(4) };
+ return CurDAG->SelectNodeTo(N, PPC::BCC, MVT::Other, Ops, 5);
+ }
case ISD::BR_CC: {
AddToISelQueue(N->getOperand(0));
ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get();
SDOperand CondCode = SelectCC(N->getOperand(2), N->getOperand(3), CC);
- SDOperand Ops[] = { CondCode, getI32Imm(getPredicateForSetCC(CC)),
+ SDOperand Ops[] = { getI32Imm(getPredicateForSetCC(CC)), CondCode,
N->getOperand(4), N->getOperand(0) };
return CurDAG->SelectNodeTo(N, PPC::BCC, MVT::Other, Ops, 4);
}
Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.230 llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.231
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.230 Fri Nov 17 16:14:47 2006
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp Fri Nov 17 16:37:34 2006
@@ -2614,7 +2614,7 @@
MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB);
unsigned SelectPred = MI->getOperand(4).getImm();
BuildMI(BB, PPC::BCC, 3)
- .addReg(MI->getOperand(1).getReg()).addImm(SelectPred).addMBB(sinkMBB);
+ .addImm(SelectPred).addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB);
MachineFunction *F = BB->getParent();
F->getBasicBlockList().insert(It, copy0MBB);
F->getBasicBlockList().insert(It, sinkMBB);
@@ -2890,8 +2890,8 @@
}
return DAG.getNode(PPCISD::COND_BRANCH, MVT::Other, N->getOperand(0),
- DAG.getRegister(PPC::CR6, MVT::i32),
DAG.getConstant(CompOpc, MVT::i32),
+ DAG.getRegister(PPC::CR6, MVT::i32),
N->getOperand(4), CompNode.getValue(1));
}
break;
Index: llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
diff -u llvm/lib/Target/PowerPC/PPCInstrInfo.cpp:1.33 llvm/lib/Target/PowerPC/PPCInstrInfo.cpp:1.34
--- llvm/lib/Target/PowerPC/PPCInstrInfo.cpp:1.33 Fri Nov 17 16:14:47 2006
+++ llvm/lib/Target/PowerPC/PPCInstrInfo.cpp Fri Nov 17 16:37:34 2006
@@ -260,13 +260,13 @@
BuildMI(&MBB, PPC::B, 1).addMBB(TBB);
else // Conditional branch
BuildMI(&MBB, PPC::BCC, 3)
- .addReg(Cond[0].getReg()).addImm(Cond[1].getImm()).addMBB(TBB);
+ .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
return;
}
// Two-way Conditional Branch.
BuildMI(&MBB, PPC::BCC, 3)
- .addReg(Cond[0].getReg()).addImm(Cond[1].getImm()).addMBB(TBB);
+ .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
BuildMI(&MBB, PPC::B, 1).addMBB(FBB);
}
@@ -285,6 +285,6 @@
ReverseBranchCondition(std::vector<MachineOperand> &Cond) const {
assert(Cond.size() == 2 && "Invalid PPC branch opcode!");
// Leave the CR# the same, but invert the condition.
- Cond[1].setImm(PPC::InvertPredicate((PPC::Predicate)Cond[1].getImm()));
+ Cond[0].setImm(PPC::InvertPredicate((PPC::Predicate)Cond[0].getImm()));
return false;
}
Index: llvm/lib/Target/PowerPC/PPCInstrInfo.td
diff -u llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.268 llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.269
--- llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.268 Fri Nov 17 16:14:47 2006
+++ llvm/lib/Target/PowerPC/PPCInstrInfo.td Fri Nov 17 16:37:34 2006
@@ -34,7 +34,7 @@
]>;
def SDT_PPCcondbr : SDTypeProfile<0, 3, [
- SDTCisVT<1, i32>, SDTCisVT<2, OtherVT>
+ SDTCisVT<0, i32>, SDTCisVT<2, OtherVT>
]>;
def SDT_PPClbrx : SDTypeProfile<1, 3, [
@@ -358,11 +358,12 @@
[(br bb:$dst)]>;
}
- // BCC is formed before branch selection, it is turned into Bxx below.
- // 'opc' is a 'PPC::Predicate' value.
- def BCC : Pseudo<(ops CRRC:$crS, u16imm:$opc, target:$dst),
- "${:comment} BCC $crS, $opc, $dst",
- [(PPCcondbranch CRRC:$crS, imm:$opc, bb:$dst)]>;
+ // BCC represents an arbitrary conditional branch on a predicate.
+ // FIXME: should be able to write a pattern for PPCcondbranch, but can't use
+ // a two-value operand where a dag node expects two operands. :(
+ def BCC : Pseudo<(ops pred:$cond, target:$dst),
+ "b${cond:cc} ${cond:reg}, $dst",
+ [/*(PPCcondbranch CRRC:$crS, imm:$opc, bb:$dst)*/]>;
def BLT : BForm<16, 0, 0, 12, 0, (ops CRRC:$crS, target:$block),
"blt $crS, $block", BrB>;
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