[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp PPCISelLowering.cpp PPCInstr64Bit.td PPCInstrInfo.td
Chris Lattner
sabre at nondot.org
Wed Nov 15 11:55:28 PST 2006
Changes in directory llvm/lib/Target/PowerPC:
PPCISelDAGToDAG.cpp updated: 1.219 -> 1.220
PPCISelLowering.cpp updated: 1.226 -> 1.227
PPCInstr64Bit.td updated: 1.27 -> 1.28
PPCInstrInfo.td updated: 1.260 -> 1.261
---
Log message:
fix ldu/stu jit encoding. Swith 64-bit preinc load instrs to use memri
addrmodes.
---
Diffs of the changes: (+58 -52)
PPCISelDAGToDAG.cpp | 55 ++++++++++++++++++++++++++--------------------------
PPCISelLowering.cpp | 25 ++++++++++++++++-------
PPCInstr64Bit.td | 28 +++++++++++---------------
PPCInstrInfo.td | 2 -
4 files changed, 58 insertions(+), 52 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
diff -u llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:1.219 llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:1.220
--- llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:1.219 Tue Nov 14 12:43:11 2006
+++ llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp Wed Nov 15 13:55:13 2006
@@ -828,36 +828,37 @@
if (LD->getAddressingMode() != ISD::PRE_INC)
break;
- unsigned Opcode;
- bool isSExt = LD->getExtensionType() == ISD::SEXTLOAD;
- if (LD->getValueType(0) != MVT::i64) {
- // Handle PPC32 integer and normal FP loads.
- assert(!isSExt || LoadedVT == MVT::i16 && "Invalid sext update load");
- switch (LoadedVT) {
- default: assert(0 && "Invalid PPC load type!");
- case MVT::f64: Opcode = PPC::LFDU; break;
- case MVT::f32: Opcode = PPC::LFSU; break;
- case MVT::i32: Opcode = PPC::LWZU; break;
- case MVT::i16: Opcode = isSExt ? PPC::LHAU : PPC::LHZU; break;
- case MVT::i1:
- case MVT::i8: Opcode = PPC::LBZU; break;
- }
- } else {
- assert(LD->getValueType(0) == MVT::i64 && "Unknown load result type!");
- assert(!isSExt || LoadedVT == MVT::i16 && "Invalid sext update load");
- switch (LoadedVT) {
- default: assert(0 && "Invalid PPC load type!");
- case MVT::i64: Opcode = PPC::LDU; break;
- case MVT::i32: Opcode = PPC::LWZU8; break;
- case MVT::i16: Opcode = isSExt ? PPC::LHAU8 : PPC::LHZU8; break;
- case MVT::i1:
- case MVT::i8: Opcode = PPC::LBZU8; break;
- }
- }
-
SDOperand Offset = LD->getOffset();
if (isa<ConstantSDNode>(Offset) ||
Offset.getOpcode() == ISD::TargetGlobalAddress) {
+
+ unsigned Opcode;
+ bool isSExt = LD->getExtensionType() == ISD::SEXTLOAD;
+ if (LD->getValueType(0) != MVT::i64) {
+ // Handle PPC32 integer and normal FP loads.
+ assert(!isSExt || LoadedVT == MVT::i16 && "Invalid sext update load");
+ switch (LoadedVT) {
+ default: assert(0 && "Invalid PPC load type!");
+ case MVT::f64: Opcode = PPC::LFDU; break;
+ case MVT::f32: Opcode = PPC::LFSU; break;
+ case MVT::i32: Opcode = PPC::LWZU; break;
+ case MVT::i16: Opcode = isSExt ? PPC::LHAU : PPC::LHZU; break;
+ case MVT::i1:
+ case MVT::i8: Opcode = PPC::LBZU; break;
+ }
+ } else {
+ assert(LD->getValueType(0) == MVT::i64 && "Unknown load result type!");
+ assert(!isSExt || LoadedVT == MVT::i16 && "Invalid sext update load");
+ switch (LoadedVT) {
+ default: assert(0 && "Invalid PPC load type!");
+ case MVT::i64: Opcode = PPC::LDU; break;
+ case MVT::i32: Opcode = PPC::LWZU8; break;
+ case MVT::i16: Opcode = isSExt ? PPC::LHAU8 : PPC::LHZU8; break;
+ case MVT::i1:
+ case MVT::i8: Opcode = PPC::LBZU8; break;
+ }
+ }
+
SDOperand Chain = LD->getChain();
SDOperand Base = LD->getBasePtr();
AddToISelQueue(Chain);
Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.226 llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.227
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.226 Mon Nov 13 23:28:08 2006
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp Wed Nov 15 13:55:13 2006
@@ -877,12 +877,12 @@
MVT::ValueType VT;
if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
Ptr = LD->getBasePtr();
- VT = LD->getValueType(0);
+ VT = LD->getLoadedVT();
+
} else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
ST = ST;
Ptr = ST->getBasePtr();
VT = ST->getStoredVT();
- return false; // TODO: Stores.
} else
return false;
@@ -890,18 +890,27 @@
if (MVT::isVector(VT))
return false;
- // TODO: Handle reg+reg.
- if (!SelectAddressRegImm(Ptr, Offset, Base, DAG))
- return false;
+ // TODO: Check reg+reg first.
+
+ // LDU/STU use reg+imm*4, others use reg+imm.
+ if (VT != MVT::i64) {
+ // reg + imm
+ if (!SelectAddressRegImm(Ptr, Offset, Base, DAG))
+ return false;
+ } else {
+ // reg + imm * 4.
+ if (!SelectAddressRegImmShift(Ptr, Offset, Base, DAG))
+ return false;
+ }
- // PPC64 doesn't have lwau, but it does have lwaux. Reject preinc load of
- // sext i32 to i64 when addr mode is r+i.
if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
+ // PPC64 doesn't have lwau, but it does have lwaux. Reject preinc load of
+ // sext i32 to i64 when addr mode is r+i.
if (LD->getValueType(0) == MVT::i64 && LD->getLoadedVT() == MVT::i32 &&
LD->getExtensionType() == ISD::SEXTLOAD &&
isa<ConstantSDNode>(Offset))
return false;
- }
+ }
AM = ISD::PRE_INC;
return true;
Index: llvm/lib/Target/PowerPC/PPCInstr64Bit.td
diff -u llvm/lib/Target/PowerPC/PPCInstr64Bit.td:1.27 llvm/lib/Target/PowerPC/PPCInstr64Bit.td:1.28
--- llvm/lib/Target/PowerPC/PPCInstr64Bit.td:1.27 Wed Nov 15 11:40:51 2006
+++ llvm/lib/Target/PowerPC/PPCInstr64Bit.td Wed Nov 15 13:55:13 2006
@@ -322,18 +322,15 @@
// Update forms.
-def LBZU8 : DForm_1<35, (ops G8RC:$rD, ptr_rc:$rA_result, symbolLo:$disp,
- ptr_rc:$rA),
- "lbzu $rD, $disp($rA)", LdStGeneral,
- []>, RegConstraint<"$rA = $rA_result">;
-def LHZU8 : DForm_1<41, (ops G8RC:$rD, ptr_rc:$rA_result, symbolLo:$disp,
- ptr_rc:$rA),
- "lhzu $rD, $disp($rA)", LdStGeneral,
- []>, RegConstraint<"$rA = $rA_result">;
-def LWZU8 : DForm_1<33, (ops G8RC:$rD, ptr_rc:$rA_result, symbolLo:$disp,
- ptr_rc:$rA),
- "lwzu $rD, $disp($rA)", LdStGeneral,
- []>, RegConstraint<"$rA = $rA_result">;
+def LBZU8 : DForm_1<35, (ops G8RC:$rD, ptr_rc:$ea_result, memri:$addr),
+ "lbzu $rD, $addr", LdStGeneral,
+ []>, RegConstraint<"$addr.reg = $ea_result">;
+def LHZU8 : DForm_1<41, (ops G8RC:$rD, ptr_rc:$ea_result, memri:$addr),
+ "lhzu $rD, $addr", LdStGeneral,
+ []>, RegConstraint<"$addr.reg = $ea_result">;
+def LWZU8 : DForm_1<33, (ops G8RC:$rD, ptr_rc:$ea_result, memri:$addr),
+ "lwzu $rD, $addr", LdStGeneral,
+ []>, RegConstraint<"$addr.reg = $ea_result">;
}
@@ -347,10 +344,9 @@
"ldx $rD, $src", LdStLD,
[(set G8RC:$rD, (load xaddr:$src))]>, isPPC64;
-def LDU : DSForm_1<58, 1, (ops G8RC:$rD, ptr_rc:$rA_result, symbolLo:$disp,
- ptr_rc:$rA),
- "ldu $rD, $disp($rA)", LdStLD,
- []>, RegConstraint<"$rA = $rA_result">, isPPC64;
+def LDU : DSForm_1<58, 1, (ops G8RC:$rD, ptr_rc:$ea_result, memrix:$addr),
+ "ldu $rD, $addr", LdStLD,
+ []>, RegConstraint<"$addr.reg = $ea_result">, isPPC64;
}
Index: llvm/lib/Target/PowerPC/PPCInstrInfo.td
diff -u llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.260 llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.261
--- llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.260 Tue Nov 14 20:43:19 2006
+++ llvm/lib/Target/PowerPC/PPCInstrInfo.td Wed Nov 15 13:55:13 2006
@@ -255,7 +255,7 @@
}
def memrix : Operand<iPTR> { // memri where the imm is shifted 2 bits.
let PrintMethod = "printMemRegImmShifted";
- let MIOperandInfo = (ops i32imm, ptr_rc);
+ let MIOperandInfo = (ops i32imm:$imm, ptr_rc:$reg);
}
// PowerPC Predicate operand. 20 = (0<<5)|20 = always, CR0 is a dummy reg
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