[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCHazardRecognizers.cpp PPCInstrInfo.td
Chris Lattner
sabre at nondot.org
Tue Nov 14 18:43:35 PST 2006
Changes in directory llvm/lib/Target/PowerPC:
PPCHazardRecognizers.cpp updated: 1.15 -> 1.16
PPCInstrInfo.td updated: 1.259 -> 1.260
---
Log message:
Switch loads over to use memri as the operand instead of a reg/imm operand
pair for cleanliness. Add instructions for PPC32 preinc-stores with commented
out patterns. More improvement is needed to enable the patterns, but we're
getting close.
---
Diffs of the changes: (+60 -43)
PPCHazardRecognizers.cpp | 11 ++---
PPCInstrInfo.td | 92 ++++++++++++++++++++++++++++-------------------
2 files changed, 60 insertions(+), 43 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCHazardRecognizers.cpp
diff -u llvm/lib/Target/PowerPC/PPCHazardRecognizers.cpp:1.15 llvm/lib/Target/PowerPC/PPCHazardRecognizers.cpp:1.16
--- llvm/lib/Target/PowerPC/PPCHazardRecognizers.cpp:1.15 Mon Nov 13 14:11:06 2006
+++ llvm/lib/Target/PowerPC/PPCHazardRecognizers.cpp Tue Nov 14 20:43:19 2006
@@ -234,14 +234,14 @@
unsigned ThisStoreSize;
switch (Opcode) {
default: assert(0 && "Unknown store instruction!");
- case PPC::STB:
+ case PPC::STB: case PPC::STBU:
case PPC::STBX:
case PPC::STB8:
case PPC::STBX8:
case PPC::STVEBX:
ThisStoreSize = 1;
break;
- case PPC::STH:
+ case PPC::STH: case PPC::STHU:
case PPC::STHX:
case PPC::STH8:
case PPC::STHX8:
@@ -249,12 +249,11 @@
case PPC::STHBRX:
ThisStoreSize = 2;
break;
- case PPC::STFS:
+ case PPC::STFS: case PPC::STFSU:
case PPC::STFSX:
- case PPC::STWU:
case PPC::STWX:
case PPC::STWUX:
- case PPC::STW:
+ case PPC::STW: case PPC::STWU:
case PPC::STW8:
case PPC::STWX8:
case PPC::STVEWX:
@@ -264,7 +263,7 @@
break;
case PPC::STD_32:
case PPC::STDX_32:
- case PPC::STD:
+ case PPC::STD: case PPC::STDU:
case PPC::STFD:
case PPC::STFDX:
case PPC::STDX:
Index: llvm/lib/Target/PowerPC/PPCInstrInfo.td
diff -u llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.259 llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.260
--- llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.259 Tue Nov 14 13:19:53 2006
+++ llvm/lib/Target/PowerPC/PPCInstrInfo.td Tue Nov 14 20:43:19 2006
@@ -247,7 +247,7 @@
// Address operands
def memri : Operand<iPTR> {
let PrintMethod = "printMemRegImm";
- let MIOperandInfo = (ops i32imm, ptr_rc);
+ let MIOperandInfo = (ops i32imm:$imm, ptr_rc:$reg);
}
def memrr : Operand<iPTR> {
let PrintMethod = "printMemRegReg";
@@ -270,6 +270,7 @@
def xoaddr : ComplexPattern<iPTR, 2, "SelectAddrIdxOnly",[], []>;
def ixaddr : ComplexPattern<iPTR, 2, "SelectAddrImmShift", [], []>; // "std"
+
//===----------------------------------------------------------------------===//
// PowerPC Instruction Predicate Definitions.
def FPContractions : Predicate<"!NoExcessFPPrecision">;
@@ -410,7 +411,7 @@
// PPC32 Load Instructions.
//
-// Unindexed (r+i) Loads.
+// Unindexed (r+i) Loads.
let isLoad = 1, PPC970_Unit = 2 in {
def LBZ : DForm_1<34, (ops GPRC:$rD, memri:$src),
"lbz $rD, $src", LdStGeneral,
@@ -434,38 +435,32 @@
[(set F8RC:$rD, (load iaddr:$src))]>;
-// 'Update' load forms.
-def LBZU : DForm_1<35, (ops GPRC:$rD, ptr_rc:$rA_result, symbolLo:$disp,
- ptr_rc:$rA),
- "lbzu $rD, $disp($rA)", LdStGeneral,
- []>, RegConstraint<"$rA = $rA_result">;
-
-def LHAU : DForm_1<43, (ops GPRC:$rD, ptr_rc:$rA_result, symbolLo:$disp,
- ptr_rc:$rA),
- "lhau $rD, $disp($rA)", LdStGeneral,
- []>, RegConstraint<"$rA = $rA_result">;
-
-def LHZU : DForm_1<41, (ops GPRC:$rD, ptr_rc:$rA_result, symbolLo:$disp,
- ptr_rc:$rA),
- "lhzu $rD, $disp($rA)", LdStGeneral,
- []>, RegConstraint<"$rA = $rA_result">;
-
-def LWZU : DForm_1<33, (ops GPRC:$rD, ptr_rc:$rA_result, symbolLo:$disp,
- ptr_rc:$rA),
- "lwzu $rD, $disp($rA)", LdStGeneral,
- []>, RegConstraint<"$rA = $rA_result">;
-
-def LFSU : DForm_1<49, (ops F4RC:$rD, ptr_rc:$rA_result, symbolLo:$disp,
- ptr_rc:$rA),
- "lfs $rD, $disp($rA)", LdStLFDU,
- []>, RegConstraint<"$rA = $rA_result">;
-def LFDU : DForm_1<51, (ops F8RC:$rD, ptr_rc:$rA_result, symbolLo:$disp,
- ptr_rc:$rA),
- "lfd $rD, $disp($rA)", LdStLFD,
- []>, RegConstraint<"$rA = $rA_result">;
+// Unindexed (r+i) Loads with Update (preinc).
+def LBZU : DForm_1<35, (ops GPRC:$rD, ptr_rc:$ea_result, memri:$addr),
+ "lbzu $rD, $addr", LdStGeneral,
+ []>, RegConstraint<"$addr.reg = $ea_result">;
+
+def LHAU : DForm_1<43, (ops GPRC:$rD, ptr_rc:$ea_result, memri:$addr),
+ "lhau $rD, $addr", LdStGeneral,
+ []>, RegConstraint<"$addr.reg = $ea_result">;
+
+def LHZU : DForm_1<41, (ops GPRC:$rD, ptr_rc:$ea_result, memri:$addr),
+ "lhzu $rD, $addr", LdStGeneral,
+ []>, RegConstraint<"$addr.reg = $ea_result">;
+
+def LWZU : DForm_1<33, (ops GPRC:$rD, ptr_rc:$ea_result, memri:$addr),
+ "lwzu $rD, $addr", LdStGeneral,
+ []>, RegConstraint<"$addr.reg = $ea_result">;
+
+def LFSU : DForm_1<49, (ops F4RC:$rD, ptr_rc:$ea_result, memri:$addr),
+ "lfs $rD, $addr", LdStLFDU,
+ []>, RegConstraint<"$addr.reg = $ea_result">;
+def LFDU : DForm_1<51, (ops F8RC:$rD, ptr_rc:$ea_result, memri:$addr),
+ "lfd $rD, $addr", LdStLFD,
+ []>, RegConstraint<"$addr.reg = $ea_result">;
}
-// Indexed (r+r) loads.
+// Indexed (r+r) Loads.
//
let isLoad = 1, PPC970_Unit = 2 in {
def LBZX : XForm_1<31, 87, (ops GPRC:$rD, memrr:$src),
@@ -502,7 +497,7 @@
// PPC32 Store Instructions.
//
-// Unindexed (r+i) Stores.
+// Unindexed (r+i) Stores.
let isStore = 1, noResults = 1, PPC970_Unit = 2 in {
def STB : DForm_3<38, (ops GPRC:$rS, memri:$src),
"stb $rS, $src", LdStGeneral,
@@ -513,10 +508,6 @@
def STW : DForm_3<36, (ops GPRC:$rS, memri:$src),
"stw $rS, $src", LdStGeneral,
[(store GPRC:$rS, iaddr:$src)]>;
-def STWU : DForm_3<37, (ops GPRC:$rS, s16imm:$disp, GPRC:$rA),
- "stwu $rS, $disp($rA)", LdStGeneral,
- []>;
-
def STFS : DForm_1<52, (ops F4RC:$rS, memri:$dst),
"stfs $rS, $dst", LdStUX,
[(store F4RC:$rS, iaddr:$dst)]>;
@@ -525,6 +516,33 @@
[(store F8RC:$rS, iaddr:$dst)]>;
}
+// Unindexed (r+i) Stores with Update (preinc).
+let isStore = 1, PPC970_Unit = 2 in {
+def STBU : DForm_3<39, (ops ptr_rc:$ea_res, GPRC:$rS, memri:$addr),
+ "stbu $rS, $addr", LdStGeneral,
+ [/*(set ptr_rc:$ea_res,
+ (pre_truncsti8 GPRC:$rS, iaddr:$addr))*/]>,
+ RegConstraint<"$addr.reg = $ea_res">;
+def STHU : DForm_3<37, (ops ptr_rc:$ea_res, GPRC:$rS, memri:$addr),
+ "sthu $rS, $addr", LdStGeneral,
+ [/*(set ptr_rc:$ea_res,
+ (pre_truncsti16 GPRC:$rS, iaddr:$addr))*/]>,
+ RegConstraint<"$addr.reg = $ea_res">;
+def STWU : DForm_3<37, (ops ptr_rc:$ea_res, GPRC:$rS, memri:$addr),
+ "stwu $rS, $addr", LdStGeneral,
+ [/*(set ptr_rc:$ea_res, (pre_store GPRC:$rS, iaddr:$addr))*/]>,
+ RegConstraint<"$addr.reg = $ea_res">;
+def STFSU : DForm_3<37, (ops ptr_rc:$ea_res, F4RC:$rS, memri:$addr),
+ "stfsu $rS, $addr", LdStGeneral,
+ [/*(set ptr_rc:$ea_res, (pre_store F4RC:$rS, iaddr:$addr))*/]>,
+ RegConstraint<"$addr.reg = $ea_res">;
+def STFDU : DForm_3<37, (ops ptr_rc:$ea_res, F8RC:$rS, memri:$addr),
+ "stfdu $rS, $addr", LdStGeneral,
+ [/*(set ptr_rc:$ea_res, (pre_store F8RC:$rS, iaddr:$addr))*/]>,
+ RegConstraint<"$addr.reg = $ea_res">;
+}
+
+
// Indexed (r+r) Stores.
//
let isStore = 1, noResults = 1, PPC970_Unit = 2 in {
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