[llvm-commits] CVS: llvm/utils/TableGen/DAGISelEmitter.cpp

[Chris Lattner]

Changes in directory llvm/utils/TableGen:

DAGISelEmitter.cpp updated: 1.282 -> 1.283
---
Log message:

changes to get ptr_rc to be accepted in patterns.  This is needed for ppc preinc
stores.


---
Diffs of the changes:  (+22 -8)

 DAGISelEmitter.cpp |   30 ++++++++++++++++++++++--------
 1 files changed, 22 insertions(+), 8 deletions(-)


Index: llvm/utils/TableGen/DAGISelEmitter.cpp
diff -u llvm/utils/TableGen/DAGISelEmitter.cpp:1.282 llvm/utils/TableGen/DAGISelEmitter.cpp:1.283
--- llvm/utils/TableGen/DAGISelEmitter.cpp:1.282	Tue Nov 14 12:41:38 2006
+++ llvm/utils/TableGen/DAGISelEmitter.cpp	Tue Nov 14 15:18:40 2006
@@ -618,6 +618,9 @@
     std::vector<unsigned char>
     ComplexPat(1, TP.getDAGISelEmitter().getComplexPattern(R).getValueType());
     return ComplexPat;
+  } else if (R->getName() == "ptr_rc") {
+    Other[0] = MVT::iPTR;
+    return Other;
   } else if (R->getName() == "node" || R->getName() == "srcvalue") {
     // Placeholder.
     return Unknown;
@@ -747,16 +750,23 @@
     CodeGenInstruction &InstInfo =
       ISE.getTargetInfo().getInstruction(getOperator()->getName());
     // Apply the result type to the node
-    if (NumResults == 0 || InstInfo.noResults) { // FIXME: temporary hack...
+    if (NumResults == 0 || InstInfo.noResults) { // FIXME: temporary hack.
       MadeChange = UpdateNodeType(MVT::isVoid, TP);
     } else {
       Record *ResultNode = Inst.getResult(0);
-      assert(ResultNode->isSubClassOf("RegisterClass") &&
-             "Operands should be register classes!");
+      
+      if (ResultNode->getName() == "ptr_rc") {
+        std::vector<unsigned char> VT;
+        VT.push_back(MVT::iPTR);
+        MadeChange = UpdateNodeType(VT, TP);
+      } else {
+        assert(ResultNode->isSubClassOf("RegisterClass") &&
+               "Operands should be register classes!");
 
-      const CodeGenRegisterClass &RC = 
-        ISE.getTargetInfo().getRegisterClass(ResultNode);
-      MadeChange = UpdateNodeType(ConvertVTs(RC.getValueTypes()), TP);
+        const CodeGenRegisterClass &RC = 
+          ISE.getTargetInfo().getRegisterClass(ResultNode);
+        MadeChange = UpdateNodeType(ConvertVTs(RC.getValueTypes()), TP);
+      }
     }
 
     unsigned ChildNo = 0;
@@ -782,6 +792,8 @@
       } else if (OperandNode->isSubClassOf("Operand")) {
         VT = getValueType(OperandNode->getValueAsDef("Type"));
         MadeChange |= Child->UpdateNodeType(VT, TP);
+      } else if (OperandNode->getName() == "ptr_rc") {
+        MadeChange |= Child->UpdateNodeType(MVT::iPTR, TP);
       } else {
         assert(0 && "Unknown operand type!");
         abort();
@@ -1381,7 +1393,8 @@
     if (!Val)
       I->error("set destination should be a register!");
 
-    if (Val->getDef()->isSubClassOf("RegisterClass")) {
+    if (Val->getDef()->isSubClassOf("RegisterClass") ||
+        Val->getDef()->getName() == "ptr_rc") {
       if (Dest->getName().empty())
         I->error("set destination must have a name!");
       if (InstResults.count(Dest->getName()))
@@ -2507,7 +2520,8 @@
       // Handle leaves of various types.
       if (DefInit *DI = dynamic_cast<DefInit*>(Child->getLeafValue())) {
         Record *LeafRec = DI->getDef();
-        if (LeafRec->isSubClassOf("RegisterClass")) {
+        if (LeafRec->isSubClassOf("RegisterClass") || 
+            LeafRec->getName() == "ptr_rc") {
           // Handle register references.  Nothing to do here.
         } else if (LeafRec->isSubClassOf("Register")) {
           // Handle register references.