[llvm-commits] CVS: llvm/lib/Target/ARM/ARMInstrInfo.td

[Rafael Espindola]

Changes in directory llvm/lib/Target/ARM:

ARMInstrInfo.td updated: 1.71 -> 1.72
---
Log message:

implement  zextload bool and truncstore bool


---
Diffs of the changes:  (+10 -0)

 ARMInstrInfo.td |   10 ++++++++++
 1 files changed, 10 insertions(+)


Index: llvm/lib/Target/ARM/ARMInstrInfo.td
diff -u llvm/lib/Target/ARM/ARMInstrInfo.td:1.71 llvm/lib/Target/ARM/ARMInstrInfo.td:1.72
--- llvm/lib/Target/ARM/ARMInstrInfo.td:1.71	Tue Oct 24 11:47:57 2006
+++ llvm/lib/Target/ARM/ARMInstrInfo.td	Wed Nov  1 08:13:27 2006
@@ -347,3 +347,13 @@
           (LDRB IntRegs:$addr)>;
 def : Pat<(extloadi16 IntRegs:$addr),
           (LDRH IntRegs:$addr)>;
+
+// zextload bool -> zextload byte
+def : Pat<(i32 (zextloadi1 IntRegs:$addr)), (LDRB IntRegs:$addr)>;
+def : Pat<(i32 (zextloadi1 IntRegs:$addr)), (LDRB IntRegs:$addr)>;
+
+// truncstore bool -> truncstore byte.
+def : Pat<(truncstorei1 IntRegs:$src, IntRegs:$addr),
+          (STRB IntRegs:$addr, IntRegs:$src)>;
+def : Pat<(truncstorei1 IntRegs:$src, IntRegs:$addr),
+          (STRB IntRegs:$addr, IntRegs:$src)>;