[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp X86ISelLowering.h X86InstrSSE.td
Evan Cheng
evan.cheng at apple.com
Fri Oct 27 14:08:46 PDT 2006
Changes in directory llvm/lib/Target/X86:
X86ISelLowering.cpp updated: 1.280 -> 1.281
X86ISelLowering.h updated: 1.76 -> 1.77
X86InstrSSE.td updated: 1.166 -> 1.167
---
Log message:
Fixed a significant bug where unpcklpd is incorrectly used to extract element 1 from a v2f64 value.
---
Diffs of the changes: (+25 -6)
X86ISelLowering.cpp | 11 +++++++++++
X86ISelLowering.h | 4 ++++
X86InstrSSE.td | 16 ++++++++++------
3 files changed, 25 insertions(+), 6 deletions(-)
Index: llvm/lib/Target/X86/X86ISelLowering.cpp
diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.280 llvm/lib/Target/X86/X86ISelLowering.cpp:1.281
--- llvm/lib/Target/X86/X86ISelLowering.cpp:1.280 Fri Oct 27 13:49:08 2006
+++ llvm/lib/Target/X86/X86ISelLowering.cpp Fri Oct 27 16:08:32 2006
@@ -2868,6 +2868,17 @@
return ::isSplatMask(N);
}
+/// isSplatLoMask - Return true if the specified VECTOR_SHUFFLE operand
+/// specifies a splat of zero element.
+bool X86::isSplatLoMask(SDNode *N) {
+ assert(N->getOpcode() == ISD::BUILD_VECTOR);
+
+ for (unsigned i = 0, e = N->getNumOperands(); i < e; ++i)
+ if (!isUndefOrEqual(N->getOperand(i), 0))
+ return false;
+ return true;
+}
+
/// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
/// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUF* and SHUFP*
/// instructions.
Index: llvm/lib/Target/X86/X86ISelLowering.h
diff -u llvm/lib/Target/X86/X86ISelLowering.h:1.76 llvm/lib/Target/X86/X86ISelLowering.h:1.77
--- llvm/lib/Target/X86/X86ISelLowering.h:1.76 Fri Oct 20 12:42:20 2006
+++ llvm/lib/Target/X86/X86ISelLowering.h Fri Oct 27 16:08:32 2006
@@ -225,6 +225,10 @@
/// specifies a splat of a single element.
bool isSplatMask(SDNode *N);
+ /// isSplatLoMask - Return true if the specified VECTOR_SHUFFLE operand
+ /// specifies a splat of zero element.
+ bool isSplatLoMask(SDNode *N);
+
/// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
/// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUF* and SHUFP*
/// instructions.
Index: llvm/lib/Target/X86/X86InstrSSE.td
diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.166 llvm/lib/Target/X86/X86InstrSSE.td:1.167
--- llvm/lib/Target/X86/X86InstrSSE.td:1.166 Wed Oct 25 16:35:05 2006
+++ llvm/lib/Target/X86/X86InstrSSE.td Fri Oct 27 16:08:32 2006
@@ -104,8 +104,8 @@
return X86::isSplatMask(N);
}], SHUFFLE_get_shuf_imm>;
-def SSE_splat_v2_mask : PatLeaf<(build_vector), [{
- return X86::isSplatMask(N);
+def SSE_splat_lo_mask : PatLeaf<(build_vector), [{
+ return X86::isSplatLoMask(N);
}]>;
def MOVHLPS_shuffle_mask : PatLeaf<(build_vector), [{
@@ -812,13 +812,13 @@
"movddup {$src, $dst|$dst, $src}",
[(set VR128:$dst, (v2f64 (vector_shuffle
VR128:$src, (undef),
- SSE_splat_v2_mask)))]>;
+ SSE_splat_lo_mask)))]>;
def MOVDDUPrm : S3DI<0x12, MRMSrcMem, (ops VR128:$dst, f64mem:$src),
"movddup {$src, $dst|$dst, $src}",
[(set VR128:$dst, (v2f64 (vector_shuffle
(scalar_to_vector (loadf64 addr:$src)),
(undef),
- SSE_splat_v2_mask)))]>;
+ SSE_splat_lo_mask)))]>;
// SSE2 instructions without OpSize prefix
def Int_CVTDQ2PSrr : I<0x5B, MRMSrcReg, (ops VR128:$dst, VR128:$src),
@@ -1908,10 +1908,14 @@
// Splat v2f64 / v2i64
let AddedComplexity = 10 in {
-def : Pat<(vector_shuffle (v2f64 VR128:$src), (undef), SSE_splat_v2_mask:$sm),
+def : Pat<(vector_shuffle (v2f64 VR128:$src), (undef), SSE_splat_lo_mask:$sm),
(UNPCKLPDrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
-def : Pat<(vector_shuffle (v2i64 VR128:$src), (undef), SSE_splat_v2_mask:$sm),
+def : Pat<(vector_shuffle (v2f64 VR128:$src), (undef), UNPCKH_shuffle_mask:$sm),
+ (UNPCKHPDrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
+def : Pat<(vector_shuffle (v2i64 VR128:$src), (undef), SSE_splat_lo_mask:$sm),
(PUNPCKLQDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
+def : Pat<(vector_shuffle (v2i64 VR128:$src), (undef), UNPCKH_shuffle_mask:$sm),
+ (PUNPCKHQDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
}
// Splat v4f32
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