[llvm-commits] CVS: llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp ARMRegisterInfo.cpp ARMRegisterInfo.td

[Rafael Espindola]

Changes in directory llvm/lib/Target/ARM:

ARMISelDAGToDAG.cpp updated: 1.79 -> 1.80
ARMRegisterInfo.cpp updated: 1.22 -> 1.23
ARMRegisterInfo.td updated: 1.5 -> 1.6
---
Log message:

initial support for frame pointers


---
Diffs of the changes:  (+44 -5)

 ARMISelDAGToDAG.cpp |    3 +++
 ARMRegisterInfo.cpp |   41 +++++++++++++++++++++++++++++++++++++----
 ARMRegisterInfo.td  |    5 ++++-
 3 files changed, 44 insertions(+), 5 deletions(-)


Index: llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
diff -u llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp:1.79 llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp:1.80
--- llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp:1.79	Tue Oct 24 15:15:21 2006
+++ llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp	Thu Oct 26 08:31:25 2006
@@ -91,10 +91,13 @@
   setOperationAction(ISD::VASTART,       MVT::Other, Custom);
   setOperationAction(ISD::VACOPY,            MVT::Other, Expand);
   setOperationAction(ISD::VAEND,         MVT::Other, Expand);
+  setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
 
   setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
   setOperationAction(ISD::ConstantFP, MVT::f32, Expand);
 
+  setStackPointerRegisterToSaveRestore(ARM::R13);
+
   setSchedulingPreference(SchedulingForRegPressure);
   computeRegisterProperties();
 }


Index: llvm/lib/Target/ARM/ARMRegisterInfo.cpp
diff -u llvm/lib/Target/ARM/ARMRegisterInfo.cpp:1.22 llvm/lib/Target/ARM/ARMRegisterInfo.cpp:1.23
--- llvm/lib/Target/ARM/ARMRegisterInfo.cpp:1.22	Tue Oct 17 09:34:02 2006
+++ llvm/lib/Target/ARM/ARMRegisterInfo.cpp	Thu Oct 26 08:31:25 2006
@@ -19,10 +19,20 @@
 #include "llvm/CodeGen/MachineFrameInfo.h"
 #include "llvm/CodeGen/MachineLocation.h"
 #include "llvm/Type.h"
+#include "llvm/Target/TargetOptions.h"
 #include "llvm/ADT/STLExtras.h"
 #include <iostream>
 using namespace llvm;
 
+// hasFP - Return true if the specified function should have a dedicated frame
+// pointer register.  This is true if the function has variable sized allocas or
+// if frame pointer elimination is disabled.
+//
+static bool hasFP(const MachineFunction &MF) {
+  const MachineFrameInfo *MFI = MF.getFrameInfo();
+  return NoFramePointerElim || MFI->hasVarSizedObjects();
+}
+
 ARMRegisterInfo::ARMRegisterInfo()
   : ARMGenRegisterInfo(ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP) {
 }
@@ -88,6 +98,9 @@
 void ARMRegisterInfo::
 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
                               MachineBasicBlock::iterator I) const {
+  if (hasFP(MF)) {
+    assert(0);
+  }
   MBB.erase(I);
 }
 
@@ -114,17 +127,18 @@
   Offset += StackSize;
 
   assert (Offset >= 0);
+  unsigned BaseRegister = hasFP(MF) ? ARM::R11 : ARM::R13;
   if (Offset < 4096) {
     // Replace the FrameIndex with r13
-    MI.getOperand(FrameIdx).ChangeToRegister(ARM::R13, false);
+    MI.getOperand(FrameIdx).ChangeToRegister(BaseRegister, false);
     // Replace the ldr offset with Offset
     MI.getOperand(OffIdx).ChangeToImmediate(Offset);
   } else {
     // Insert a set of r12 with the full address
     // r12 = r13 + offset
     MachineBasicBlock *MBB2 = MI.getParent();
-    BuildMI(*MBB2, II, ARM::ADD, 4, ARM::R12).addReg(ARM::R13).addImm(Offset)
-	    .addImm(0).addImm(ARMShift::LSL);
+    BuildMI(*MBB2, II, ARM::ADD, 4, ARM::R12).addReg(BaseRegister)
+      .addImm(Offset).addImm(0).addImm(ARMShift::LSL);
 
     // Replace the FrameIndex with r12
     MI.getOperand(FrameIdx).ChangeToRegister(ARM::R12, false);
@@ -140,6 +154,8 @@
   MachineFrameInfo  *MFI = MF.getFrameInfo();
   int           NumBytes = (int) MFI->getStackSize();
 
+  bool HasFP = hasFP(MF);
+
   if (MFI->hasCalls()) {
     // We reserve argument space for call sites in the function immediately on
     // entry to the current function.  This eliminates the need for add/sub
@@ -147,6 +163,10 @@
     NumBytes += MFI->getMaxCallFrameSize();
   }
 
+  if (HasFP)
+    // Add space for storing the FP
+    NumBytes += 4;
+
   // Align to 8 bytes
   NumBytes = ((NumBytes + 7) / 8) * 8;
 
@@ -155,6 +175,13 @@
   //sub sp, sp, #NumBytes
   BuildMI(MBB, MBBI, ARM::SUB, 4, ARM::R13).addReg(ARM::R13).addImm(NumBytes)
 	  .addImm(0).addImm(ARMShift::LSL);
+
+  if (HasFP) {
+    BuildMI(MBB, MBBI, ARM::str, 3)
+      .addReg(ARM::R11).addImm(0).addReg(ARM::R13);
+    BuildMI(MBB, MBBI, ARM::MOV, 3, ARM::R11).addReg(ARM::R13).addImm(0).
+      addImm(ARMShift::LSL);
+  }
 }
 
 void ARMRegisterInfo::emitEpilogue(MachineFunction &MF,
@@ -166,6 +193,12 @@
   MachineFrameInfo *MFI = MF.getFrameInfo();
   int          NumBytes = (int) MFI->getStackSize();
 
+  if (hasFP(MF)) {
+    BuildMI(MBB, MBBI, ARM::MOV, 3, ARM::R13).addReg(ARM::R11).addImm(0).
+      addImm(ARMShift::LSL);
+    BuildMI(MBB, MBBI, ARM::ldr, 2, ARM::R11).addImm(0).addReg(ARM::R13);
+  }
+
   //add sp, sp, #NumBytes
   BuildMI(MBB, MBBI, ARM::ADD, 4, ARM::R13).addReg(ARM::R13).addImm(NumBytes)
 	  .addImm(0).addImm(ARMShift::LSL);
@@ -176,7 +209,7 @@
 }
 
 unsigned ARMRegisterInfo::getFrameRegister(MachineFunction &MF) const {
-  return ARM::R13;
+  return hasFP(MF) ? ARM::R11 : ARM::R13;
 }
 
 #include "ARMGenRegisterInfo.inc"


Index: llvm/lib/Target/ARM/ARMRegisterInfo.td
diff -u llvm/lib/Target/ARM/ARMRegisterInfo.td:1.5 llvm/lib/Target/ARM/ARMRegisterInfo.td:1.6
--- llvm/lib/Target/ARM/ARMRegisterInfo.td:1.5	Mon Oct  2 14:30:56 2006
+++ llvm/lib/Target/ARM/ARMRegisterInfo.td	Thu Oct 26 08:31:25 2006
@@ -125,7 +125,10 @@
       // r12 == ip (scratch)
       // r11 == Frame Pointer
       // r10 == Stack Limit
-      return end() - 4;
+      if (hasFP(MF))
+        return end() - 5;
+      else
+        return end() - 4;
     }
   }];
 }