[llvm-commits] CVS: llvm/lib/Target/ARM/ARMInstrInfo.cpp ARMInstrInfo.h ARMInstrInfo.td

[Chris Lattner]

Changes in directory llvm/lib/Target/ARM:

ARMInstrInfo.cpp updated: 1.7 -> 1.8
ARMInstrInfo.h updated: 1.3 -> 1.4
ARMInstrInfo.td updated: 1.70 -> 1.71
---
Log message:

implement uncond branch insertion, mark branches with isBranch.




---
Diffs of the changes:  (+13 -1)

 ARMInstrInfo.cpp |    8 ++++++++
 ARMInstrInfo.h   |    4 ++++
 ARMInstrInfo.td  |    2 +-
 3 files changed, 13 insertions(+), 1 deletion(-)


Index: llvm/lib/Target/ARM/ARMInstrInfo.cpp
diff -u llvm/lib/Target/ARM/ARMInstrInfo.cpp:1.7 llvm/lib/Target/ARM/ARMInstrInfo.cpp:1.8
--- llvm/lib/Target/ARM/ARMInstrInfo.cpp:1.7	Wed Sep 13 07:09:43 2006
+++ llvm/lib/Target/ARM/ARMInstrInfo.cpp	Tue Oct 24 11:47:57 2006
@@ -48,3 +48,11 @@
   }
   return false;
 }
+
+void ARMInstrInfo::InsertBranch(MachineBasicBlock &MBB,MachineBasicBlock *TBB,
+                                  MachineBasicBlock *FBB,
+                                  const std::vector<MachineOperand> &Cond)const{
+  // Can only insert uncond branches so far.
+  assert(Cond.empty() && !FBB && TBB && "Can only handle uncond branches!");
+  BuildMI(&MBB, ARM::b, 1).addMBB(TBB);
+}
\ No newline at end of file


Index: llvm/lib/Target/ARM/ARMInstrInfo.h
diff -u llvm/lib/Target/ARM/ARMInstrInfo.h:1.3 llvm/lib/Target/ARM/ARMInstrInfo.h:1.4
--- llvm/lib/Target/ARM/ARMInstrInfo.h:1.3	Tue Aug  8 15:35:03 2006
+++ llvm/lib/Target/ARM/ARMInstrInfo.h	Tue Oct 24 11:47:57 2006
@@ -40,6 +40,10 @@
   ///
   virtual bool isMoveInstr(const MachineInstr &MI,
                            unsigned &SrcReg, unsigned &DstReg) const;
+
+  virtual void InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
+                            MachineBasicBlock *FBB,
+                            const std::vector<MachineOperand> &Cond) const;
 };
 
 }


Index: llvm/lib/Target/ARM/ARMInstrInfo.td
diff -u llvm/lib/Target/ARM/ARMInstrInfo.td:1.70 llvm/lib/Target/ARM/ARMInstrInfo.td:1.71
--- llvm/lib/Target/ARM/ARMInstrInfo.td:1.70	Mon Oct 23 15:34:26 2006
+++ llvm/lib/Target/ARM/ARMInstrInfo.td	Tue Oct 24 11:47:57 2006
@@ -227,7 +227,7 @@
   def UMULL   : IntBinOp<"umull r12,", mulhu>;
 }
 
-let isTerminator = 1 in {
+let isTerminator = 1, isBranch = 1 in {
   def bcond   : InstARM<(ops brtarget:$dst, CCOp:$cc),
 	                    "b$cc $dst",
 		            [(armbr bb:$dst, imm:$cc)]>;