[llvm-commits] [SignlessTypes] CVS: llvm/lib/Target/CBackend/Writer.cpp
Zhou Sheng
zhousheng00 at gmail.com
Mon Oct 23 11:13:58 PDT 2006
Changes in directory llvm/lib/Target/CBackend:
Writer.cpp updated: 1.272.2.5 -> 1.272.2.6
---
Log message:
---
Diffs of the changes: (+11 -4)
Writer.cpp | 15 +++++++++++----
1 files changed, 11 insertions(+), 4 deletions(-)
Index: llvm/lib/Target/CBackend/Writer.cpp
diff -u llvm/lib/Target/CBackend/Writer.cpp:1.272.2.5 llvm/lib/Target/CBackend/Writer.cpp:1.272.2.6
--- llvm/lib/Target/CBackend/Writer.cpp:1.272.2.5 Sun Oct 22 04:55:50 2006
+++ llvm/lib/Target/CBackend/Writer.cpp Mon Oct 23 13:13:27 2006
@@ -586,10 +586,12 @@
case Instruction::Add:
case Instruction::Sub:
case Instruction::Mul:
+ case Instruction::URem:
+ case Instruction::SRem:
case Instruction::SDiv:
case Instruction::UDiv:
case Instruction::FDiv:
- case Instruction::Rem:
+ case Instruction::FRem:
case Instruction::And:
case Instruction::Or:
case Instruction::Xor:
@@ -607,10 +609,12 @@
case Instruction::Add: Out << " + "; break;
case Instruction::Sub: Out << " - "; break;
case Instruction::Mul: Out << " * "; break;
+ case Instruction::URem:
+ case Instruction::SRem:
+ case Instruction::FRem: Out << " % "; break;
case Instruction::UDiv:
case Instruction::SDiv:
case Instruction::FDiv: Out << " / "; break;
- case Instruction::Rem: Out << " % "; break;
case Instruction::And: Out << " & "; break;
case Instruction::Or: Out << " | "; break;
case Instruction::Xor: Out << " ^ "; break;
@@ -1634,7 +1638,8 @@
Out << "-(";
writeOperand(BinaryOperator::getNegArgument(cast<BinaryOperator>(&I)));
Out << ")";
- } else if (I.getOpcode() == Instruction::Rem &&
+ } else if ((I.getOpcode() == Instruction::URem ||
+ I.getOpcode() == Instruction::SRem) &&
I.getType()->isFloatingPoint()) {
// Output a call to fmod/fmodf instead of emitting a%b
if (I.getType() == Type::FloatTy)
@@ -1652,10 +1657,12 @@
case Instruction::Add: Out << " + "; break;
case Instruction::Sub: Out << " - "; break;
case Instruction::Mul: Out << '*'; break;
+ case Instruction::URem:
+ case Instruction::SRem:
+ case Instruction::FRem: Out << '%'; break;
case Instruction::UDiv:
case Instruction::SDiv:
case Instruction::FDiv: Out << '/'; break;
- case Instruction::Rem: Out << '%'; break;
case Instruction::And: Out << " & "; break;
case Instruction::Or: Out << " | "; break;
case Instruction::Xor: Out << " ^ "; break;
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