[llvm-commits] CVS: llvm/lib/Target/ARM/ARMInstrInfo.td ARMRegisterInfo.cpp

[Rafael Espindola]

Changes in directory llvm/lib/Target/ARM:

ARMInstrInfo.td updated: 1.58 -> 1.59
ARMRegisterInfo.cpp updated: 1.20 -> 1.21
---
Log message:

add FCPYS and FCPYD


---
Diffs of the changes:  (+16 -3)

 ARMInstrInfo.td     |    5 +++++
 ARMRegisterInfo.cpp |   14 +++++++++++---
 2 files changed, 16 insertions(+), 3 deletions(-)


Index: llvm/lib/Target/ARM/ARMInstrInfo.td
diff -u llvm/lib/Target/ARM/ARMInstrInfo.td:1.58 llvm/lib/Target/ARM/ARMInstrInfo.td:1.59
--- llvm/lib/Target/ARM/ARMInstrInfo.td:1.58	Mon Oct 16 16:50:04 2006
+++ llvm/lib/Target/ARM/ARMInstrInfo.td	Tue Oct 17 08:13:23 2006
@@ -212,6 +212,11 @@
 	               "fcmpd $a, $b",
 		       [(armcmp DFPRegs:$a, DFPRegs:$b)]>;
 
+// Floating Point Copy
+def FCPYS   : InstARM<(ops FPRegs:$dst, FPRegs:$src), "fcpys $dst, $src", []>;
+
+def FCPYD   : InstARM<(ops DFPRegs:$dst, DFPRegs:$src), "fcpyd $dst, $src", []>;
+
 // Floating Point Conversion
 // We use bitconvert for moving the data between the register classes.
 // The format conversion is done with ARM specific nodes


Index: llvm/lib/Target/ARM/ARMRegisterInfo.cpp
diff -u llvm/lib/Target/ARM/ARMRegisterInfo.cpp:1.20 llvm/lib/Target/ARM/ARMRegisterInfo.cpp:1.21
--- llvm/lib/Target/ARM/ARMRegisterInfo.cpp:1.20	Fri Oct  6 09:29:47 2006
+++ llvm/lib/Target/ARM/ARMRegisterInfo.cpp	Tue Oct 17 08:13:23 2006
@@ -47,9 +47,17 @@
                                      MachineBasicBlock::iterator I,
                                      unsigned DestReg, unsigned SrcReg,
                                      const TargetRegisterClass *RC) const {
-  assert (RC == ARM::IntRegsRegisterClass);
-  BuildMI(MBB, I, ARM::MOV, 3, DestReg).addReg(SrcReg).addImm(0)
-	  .addImm(ARMShift::LSL);
+  assert(RC == ARM::IntRegsRegisterClass ||
+         RC == ARM::FPRegsRegisterClass  ||
+         RC == ARM::DFPRegsRegisterClass);
+
+  if (RC == ARM::IntRegsRegisterClass)
+    BuildMI(MBB, I, ARM::MOV, 3, DestReg).addReg(SrcReg).addImm(0)
+      .addImm(ARMShift::LSL);
+  else if (RC == ARM::FPRegsRegisterClass)
+    BuildMI(MBB, I, ARM::FCPYS, 1, DestReg).addReg(SrcReg);
+  else
+    BuildMI(MBB, I, ARM::FCPYD, 1, DestReg).addReg(SrcReg);
 }
 
 MachineInstr *ARMRegisterInfo::foldMemoryOperand(MachineInstr* MI,